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From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 29 19:04:04 CET 2006
Subject: [cvs-checkins] MODIFIED: ae18 ...
Date: 00/06/12 29:19:04

Modified: ae18/rtl/verilog ae18_aram.v
Log:
*** empty log message ***


Revision Changes Path
1.2 ae18/rtl/verilog/ae18_aram.v

http://www.opencores.org/cvsweb.shtml/ae18/rtl/verilog/ae18_aram.v.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: ae18_aram.v
===================================================================
RCS file: /cvsroot/sybreon/ae18/rtl/verilog/ae18_aram.v,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- ae18_aram.v 29 Dec 2006 08:17:16 -0000 1.1
+++ ae18_aram.v 29 Dec 2006 18:04:04 -0000 1.2
@@ -6,11 +6,11 @@
// Last Modified By: Shawn Tan
// Last Modified On: 2006-12-29
// Update Count : 0
-// Status : Unknown, Use with caution!
+// Status : Beta/Stable

/*
*
- * $Id: ae18_aram.v,v 1.1 2006/12/29 08:17:16 sybreon Exp $
+ * $Id: ae18_aram.v,v 1.2 2006/12/29 18:04:04 sybreon Exp $
*
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
@@ -31,8 +31,9 @@
* DESCRIPTION
* Basic asynchronous inferred RAM.
*
- * 2006-12-29
- * Initial Checkin
+ * HISTORY
+ * $Log
+ *
*/

module ae18_aram (/*AUTOARG*/