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From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 29 18:52:14 CET 2006
Subject: [cvs-checkins] MODIFIED: ae18 ...
Date: 00/06/12 29:18:52

Modified: ae18/rtl/verilog ae18_core.v
Log:
Minor bug fix for PCL read/write




Revision Changes Path
1.3 ae18/rtl/verilog/ae18_core.v

http://www.opencores.org/cvsweb.shtml/ae18/rtl/verilog/ae18_core.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: ae18_core.v
===================================================================
RCS file: /cvsroot/sybreon/ae18/rtl/verilog/ae18_core.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- ae18_core.v 29 Dec 2006 08:17:16 -0000 1.2
+++ ae18_core.v 29 Dec 2006 17:52:13 -0000 1.3
@@ -9,7 +9,7 @@
// Status : Beta/Stable

/*
- * $Id: ae18_core.v,v 1.2 2006/12/29 08:17:16 sybreon Exp $
+ * $Id: ae18_core.v,v 1.3 2006/12/29 17:52:13 sybreon Exp $
*
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
@@ -1096,33 +1096,6 @@
endcase // case(rMXBCC)
end

- // SKIP register
- wire wSKP =
- (rMXSKP == MXSKP_SZ) ? wZ :
- (rMXSKP == MXSKP_SNZ) ? ~wZ :
- (rMXSKP == MXSKP_SNC) ? ~wC :
- (rMXSKP == MXSKP_SCC) ? rBCC :
- (rMXSKP == MXSKP_SU) ? 1'b1 :
- 1'b0;
- always @(negedge clk or negedge qrst)
- if (!qrst)
- rNSKP <= 1'h1;
- else if (qena[3])
- rNSKP <= #1 (rNSKP) ? ~wSKP : 1'b1;
-
- // STACK
- wire [ISIZ-1:0] wSTKW = {rTOSU,rTOSH,rTOSL};
- wire [ISIZ-1:0] wSTKR;
- wire wSTKE = (qena[1]);
-
- ae18_aram #(ISIZ,5)
- stack (
- .wdat(wSTKW), .rdat(wSTKR),
- .radr(rSTKPTR[4:0]), .wadr(rSTKPTR_[4:0]),
- .we(wSTKE),
- // Inputs
- .clk (clk));
-
/*
* DESCRIPTION
* Data WB logic
@@ -1596,4 +1569,31 @@
{rPCNXT,1'b0};
end

+ // SKIP register
+ wire wSKP =
+ (rMXSKP == MXSKP_SZ) ? wZ :
+ (rMXSKP == MXSKP_SNZ) ? ~wZ :
+ (rMXSKP == MXSKP_SNC) ? ~wC :
+ (rMXSKP == MXSKP_SCC) ? rBCC :
+ (rMXSKP == MXSKP_SU) ? (1'b1) :
+ 1'b0;
+ always @(negedge clk or negedge qrst)
+ if (!qrst)
+ rNSKP <= 1'h1;
+ else if (qena[3])
+ rNSKP <= #1 ((rDWBADR == aPCL) & rDWBWE) ? 1'b0 : ~(wSKP & rNSKP);
+
+ // STACK
+ wire [ISIZ-1:0] wSTKW = {rTOSU,rTOSH,rTOSL};
+ wire [ISIZ-1:0] wSTKR;
+ wire wSTKE = (qena[1]);
+
+ ae18_aram #(ISIZ,5)
+ stack (
+ .wdat(wSTKW), .rdat(wSTKR),
+ .radr(rSTKPTR[4:0]), .wadr(rSTKPTR_[4:0]),
+ .we(wSTKE),
+ // Inputs
+ .clk (clk));
+
endmodule // ae18_core