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From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 29 17:13:20 CET 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/12 29:17:13

Modified: jop/asm/src jvm_long.inc
Log:
laload, lastore enabled again (plus length from handle)


Revision Changes Path
1.7 jop/asm/src/jvm_long.inc

http://www.opencores.org/cvsweb.shtml/jop/asm/src/jvm_long.inc.diff?r1=1.6&r2=1.7

(In the diff below, changes in quantity of whitespace are not shown.)

Index: jvm_long.inc
===================================================================
RCS file: /cvsroot/martin/jop/asm/src/jvm_long.inc,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- jvm_long.inc 4 Nov 2006 23:28:01 -0000 1.6
+++ jvm_long.inc 29 Dec 2006 16:13:20 -0000 1.7
@@ -165,7 +165,7 @@
wait
wait
ldmrd // read ext. mem
-long_write:
+
dup

stmwa // write ext. mem address
@@ -208,12 +208,22 @@
nop opd
ld_opd_16u // CP index is the offset for the field
add // +objectref
- // address!=0 for the bnz
+
dup
- bnz long_read
- nop
- nop

+ stmra
+ ldi 1
+ add
+ stm a
+ wait
+ wait
+ ldmrd // read high word
+
+ ldm a
+ stmra
+ wait
+ wait
+ ldmrd nxt // read low word


putfield_long:
@@ -246,127 +256,128 @@
nop opd
ld_opd_16u // CP index is the offset for the field
add // +objectref
- // address!=0 for the bnz
+
dup
- bnz long_write
+
+ stmwa // write ext. mem address
+ ldm a // restore value
+ stmwd // write ext. mem data
+ ldi 1
+ add
+ wait
+ wait
+
+ stmwa
+ ldm b
+ stmwd
+ wait
+ wait
+ nop nxt
+
+lastore:
+ stm a // value_h
+ stm c // value_l
+ stm b // index
+ // arrayref is TOS
+ dup // for null pointer check
+ dup // for bound check, one cycle wait for bz
+ bz null_pointer //
+ // we do the following in the
+ // branch slot -> one more element
+ // from the former dup on the stack
+ ldi 1
+ add // arrayref+1
+ stmra // read ext. mem, mem_bsy comes one cycle later
+ wait // is this ok? - wait in branch slot
+ wait
+ ldmrd // read ext. mem (array length)
+
+ ldi 1
+ sub // length-1
+ ldm b // index + sub // TOS = length-1-index + ldm b // check if index is negativ + or // is one of both checks neagtv? + ldi -2147483648 // 0x80000000 + and + nop + bnz array_bound + nop + nop + + stmra // read handle indirection + wait // for the GC + wait + ldmrd + ldm b + ldi 1 + shl // index*2 + add // index*2+arrayref + stm d + ldm d + stmwa // write ext. mem address + ldm c + stmwd // write ext. mem data + ldm d + ldi 1 + add // index*2+arrayref+1 + wait + wait + stmwa // write ext. mem address + ldm a + stmwd // write ext. mem data + wait + wait + nop nxt + +laload: + stm b // index + // arrayref is TOS + dup // for null pointer check + dup // for bound check, one cycle wait for bz + bz null_point // we do the following in the + // branch slot -> one more element + // from the former dup on the stack + ldi 1 + add // arrayref+1 + + stmra // read array length + wait // is this ok? - wait in branch slot + wait + ldmrd // read ext. mem (array length)er // + + ldi 1 + sub // length-1 + ldm b // index + sub // TOS = length-1-index + ldm b // check if index is negative + or // is one of both checks negative? + ldi -2147483648 // 0x80000000 + and + nop + bnz array_bound nop nop + stmra // read handle indirection + wait // for the GC + wait + ldmrd + ldm b + ldi 1 + shl // index*2 + add // index*2+arrayref + dup + stm d + stmra // read ext. mem, mem_bsy comes one cycle later + wait + wait + ldmrd + ldm d + ldi 1 + add // index*2+arrayref+1 + stmra // read ext. mem, mem_bsy comes one cycle later + wait + wait + ldmrd nxt // read ext. mem -// see also the little optimizations in iaload/iastore -// -// long array access disabled: -// 1. we run out of microcode memory -// 2. we need to add long array support in the GC: -// copy the right size (add type info) -// -//lastore: -// stm a // value_h -// stm c // value_l -// stm b // index -// // arrayref is TOS -// dup // for null pointer check -// nop // wait one cycle for flags of ref -// bz null_pointer // -// nop -// nop -// -// dup // bound check -// ldi 1 -// add // arrayref+1 -// stmra // read ext. mem, mem_bsy comes one cycle later -// wait // is this ok? - wait in branch slot -// wait -// ldmrd // read ext. mem (array length) -// -// ldi 1 -// sub // length-1 -// ldm b // index -// sub // TOS = length-1-index -// ldm b // check if index is negativ -// or // is one of both checks neagtv? -// ldi -2147483648 // 0x80000000 -// and -// nop -// bnz array_bound -// nop -// nop -// -// stmra // read handle indirection -// wait // for the GC -// wait -// ldmrd -// ldm b -// ldi 1 -// shl // index*2 -// add // index*2+arrayref -// stm d -// ldm d -// stmwa // write ext. mem address -// ldm c -// stmwd // write ext. mem data -// ldm d -// ldi 1 -// add // index*2+arrayref+1 -// wait -// wait -// stmwa // write ext. mem address -// ldm a -// stmwd // write ext. mem data -// wait -// wait -// nop nxt -// -//laload: -// stm b // index -// // arrayref is TOS -// dup // for null pointer check -// nop // wait one cycle for flags of ref -// bz null_pointer // -// nop -// nop -// -// dup // for bound check -// ldi 1 -// add // arrayref+1 -// -// stmra // read array length -// wait // is this ok? - wait in branch slot -// wait -// ldmrd // read ext. mem (array length) -// -// ldi 1 -// sub // length-1 -// ldm b // index -// sub // TOS = length-1-index -// ldm b // check if index is negative -// or // is one of both checks negative? -// ldi -2147483648 // 0x80000000 -// and -// nop -// bnz array_bound -// nop -// nop -// -// stmra // read handle indirection -// wait // for the GC -// wait -// ldmrd -// ldm b -// ldi 1 -// shl // index*2 -// add // index*2+arrayref -// dup -// stm d -// stmra // read ext. mem, mem_bsy comes one cycle later -// wait -// wait -// ldmrd -// ldm d -// ldi 1 -// add // index*2+arrayref+1 -// stmra // read ext. mem, mem_bsy comes one cycle later -// wait -// wait -// ldmrd nxt // read ext. mem -//