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Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 29 15:10:36 CET 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/12 29:15:10 Modified: jop/vhdl/simulation sim_rom.vhd
Log:
use generic for pc_width
Revision Changes Path
1.2 jop/vhdl/simulation/sim_rom.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/simulation/sim_rom.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: sim_rom.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/simulation/sim_rom.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- sim_rom.vhd 11 May 2005 16:55:14 -0000 1.1
+++ sim_rom.vhd 29 Dec 2006 14:10:36 -0000 1.2
@@ -16,7 +16,7 @@
generic (width : integer; addr_width : integer);
port (
clk : in std_logic;
- address : in std_logic_vector(9 downto 0);
+ address : in std_logic_vector(addr_width-1 downto 0);
q : out std_logic_vector(9 downto 0)
);
@@ -30,7 +30,7 @@
shared variable ram : ram_type;
- signal areg : std_logic_vector(9 downto 0);
+ signal areg : std_logic_vector(addr_width-1 downto 0);
signal data : std_logic_vector(9 downto 0);
begin
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