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Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 29 14:48:05 CET 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/12 29:14:48 Modified: jop/vhdl/core fetch.vhd
Log:
removed component declaration of bcfetbl
Revision Changes Path
1.5 jop/vhdl/core/fetch.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/core/fetch.vhd.diff?r1=1.4&r2=1.5
(In the diff below, changes in quantity of whitespace are not shown.)
Index: fetch.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/core/fetch.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- fetch.vhd 5 Feb 2005 17:02:48 -0000 1.4
+++ fetch.vhd 29 Dec 2006 13:48:04 -0000 1.5
@@ -43,8 +43,8 @@
entity fetch is
generic (
- pc_width : integer := 10; -- address bits of internal instruction rom
- i_width : integer := 8 -- instruction width
+ pc_width : integer; -- address bits of internal instruction rom
+ i_width : integer -- instruction width
);
port (
clk, reset : in std_logic;
@@ -87,17 +87,6 @@
);
end component;
---
--- table to generate jfetch and jopdfetch
--- generated from Jopa.java
---
-component bcfetbl is
-port (
- addr : in std_logic_vector(pc_width-1 downto 0);
- nxt, opd : out std_logic
-);
-end component;
-
signal pc_mux : std_logic_vector(pc_width-1 downto 0);
signal pc_inc : std_logic_vector(pc_width-1 downto 0);
signal pc : std_logic_vector(pc_width-1 downto 0);
@@ -123,9 +112,6 @@
jfetch <= rom_data(9);
jopdfetch <= rom_data(8);
--- not used anymore
--- cmp_bft: bcfetbl port map(pc, jfetch, jopdfetch);
-
cmp_off: offtbl port map(ir(4 downto 0), off);
dout <= ir;
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