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From: cvs at opencores.org<cvs@o...>
Date: Wed Nov 29 13:08:38 CET 2006
Subject: [cvs-checkins] MODIFIED: CVSROOT ...

Date: 00/06/11 29:13:08

Added: CVSROOT/VHDL/VirtexE long_shiftreg.vhd Log: Long shift register for VirtexE and Spartan3 added The counters of RC5KeyBreaker were slightly modified because this last version was constraining the operating frequency Revision Changes Path 1.1 CVSROOT/VHDL/VirtexE/long_shiftreg.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/VirtexE/long_shiftreg.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: long_shiftreg.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 27/11/2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library UNISIM; use UNISIM.VComponents.all; entity long_shiftreg is generic( depthA : integer := 4; -- depth of shift register A (between 4 and 259) depthB : integer := 4); -- depth of shift register B (between 4 and 259) port( clk : in std_logic; A_in : in std_logic_vector (31 downto 0); B_in : in std_logic_vector (31 downto 0); A_out : out std_logic_vector (31 downto 0); B_out : out std_logic_vector (31 downto 0)); end long_shiftreg; architecture long_shiftreg_arch_VirtexE of long_shiftreg is constant n : integer := 32; constant ShRegStyleThreshold : integer := 3; component delay_shiftreg generic( n : integer; delay : integer); port( clk : in std_logic; sig_in : in std_logic_vector (n-1 downto 0); sig_out : out std_logic_vector (n-1 downto 0)); end component; begin gen_smallShReg: if (depthA < ShRegStyleThreshold) or (depthB < ShRegStyleThreshold) generate begin ShRagA: delay_shiftreg generic map(n,depthA) port map(clk,A_in,A_out); ShRagB: delay_shiftreg generic map(n,depthB) port map(clk,B_in,B_out); end generate; gen_bigShReg: if not((depthA < ShRegStyleThreshold) or (depthB < ShRegStyleThreshold)) generate signal DO1A,DO1B,DO2A,DO2B,DI1A,DI1B,DI2A,DI2B : std_logic_vector(15 downto 0); signal ADDR1r,ADDR1w,ADDR2r,ADDR2w : std_logic_vector(7 downto 0); begin -- port B is used for the LSBs DI1B <= A_in(15 downto 0); DI1A <= A_in(31 downto 16); DI2B <= B_in(15 downto 0); DI2A <= B_in(31 downto 16); A_out(15 downto 0) <= DO1B; A_out(31 downto 16) <= DO1A; B_out(15 downto 0) <= DO2B; B_out(31 downto 16) <= DO2A; gen_equal_depth: if (depthA = depthB) generate signal ABcounter : std_logic_vector(8 downto 0):=(others=>'1'); begin proc_countAB: process(clk) begin if rising_edge(clk) then if (ABcounter(8) = '1') then -- if ABcounter < 0 (2's complement) ABcounter <= CONV_STD_LOGIC_VECTOR(depthA - 2, 9); else ABcounter <= ABcounter - 1; end if; ADDR1w <= ADDR1r; ADDR2w <= ADDR2r; end if; end process; ADDR1r <= ABcounter(7 downto 0); ADDR2r <= ABcounter(7 downto 0); end generate; gen_notequal_depth: if not(depthA = depthB) generate signal Acounter,Bcounter : std_logic_vector(8 downto 0):=(others=>'1'); begin proc_countA: process(clk) begin if rising_edge(clk) then if (Acounter(8) = '1') then -- if ABcounter < 0 (2's complement) Acounter <= CONV_STD_LOGIC_VECTOR(depthA - 2, 9); else Acounter <= Acounter - 1; end if; ADDR1w <= ADDR1r; end if; end process; proc_countB: process(clk) begin if rising_edge(clk) then if (Bcounter(8) = '1') then -- if ABcounter < 0 (2's complement) Bcounter <= CONV_STD_LOGIC_VECTOR(depthB - 2, 9); else Bcounter <= Bcounter - 1; end if; ADDR2w <= ADDR2r; end if; end process; ADDR1r <= Acounter(7 downto 0); ADDR2r <= Bcounter(7 downto 0); end generate; -- RAMB4_S16_S16: Virtex/E, Spartan-II/IIE 256 x 16 Dual-Port RAM -- Xilinx HDL Language Template version 8.1i RAMB4_S16_S16_inst1B : RAMB4_S16_S16 port map ( DOA => open, -- Port A 16-bit data output DOB => DO1B, -- Port B 16-bit data output ADDRA => ADDR1w, -- Port A 8-bit address input ADDRB => ADDR1r, -- Port B 8-bit address input CLKA => clk, -- Port A clock input CLKB => clk, -- Port B clock input DIA => DI1B, -- Port A 16-bit data input DIB => (others=>'0'), -- Port B 16-bit data input ENA => '1', -- Port A RAM enable input ENB => '1', -- Port B RAM enable input RSTA => '0', -- Port A Synchronous reset input RSTB => '0', -- Port B Synchronous reset input WEA => '1', -- Port A RAM write enable input WEB => '0' -- Port B RAM write enable input ); -- End of RAMB4_S16_S16_inst1 instantiation -- RAMB4_S16_S16: Virtex/E, Spartan-II/IIE 256 x 16 Dual-Port RAM -- Xilinx HDL Language Template version 8.1i RAMB4_S16_S16_inst1A : RAMB4_S16_S16 port map ( DOA => open, -- Port A 16-bit data output DOB => DO1A, -- Port B 16-bit data output ADDRA => ADDR1w, -- Port A 8-bit address input ADDRB => ADDR1r, -- Port B 8-bit address input CLKA => clk, -- Port A clock input CLKB => clk, -- Port B clock input DIA => DI1A, -- Port A 16-bit data input DIB => (others=>'0'), -- Port B 16-bit data input ENA => '1', -- Port A RAM enable input ENB => '1', -- Port B RAM enable input RSTA => '0', -- Port A Synchronous reset input RSTB => '0', -- Port B Synchronous reset input WEA => '1', -- Port A RAM write enable input WEB => '0' -- Port B RAM write enable input ); -- End of RAMB4_S16_S16_inst2 instantiation -- RAMB4_S16_S16: Virtex/E, Spartan-II/IIE 256 x 16 Dual-Port RAM -- Xilinx HDL Language Template version 8.1i RAMB4_S16_S16_inst2B : RAMB4_S16_S16 port map ( DOA => open, -- Port A 16-bit data output DOB => DO2B, -- Port B 16-bit data output ADDRA => ADDR2w, -- Port A 8-bit address input ADDRB => ADDR2r, -- Port B 8-bit address input CLKA => clk, -- Port A clock input CLKB => clk, -- Port B clock input DIA => DI2B, -- Port A 16-bit data input DIB => (others=>'0'), -- Port B 16-bit data input ENA => '1', -- Port A RAM enable input ENB => '1', -- Port B RAM enable input RSTA => '0', -- Port A Synchronous reset input RSTB => '0', -- Port B Synchronous reset input WEA => '1', -- Port A RAM write enable input WEB => '0' -- Port B RAM write enable input ); -- End of RAMB4_S16_S16_inst2 instantiation -- RAMB4_S16_S16: Virtex/E, Spartan-II/IIE 256 x 16 Dual-Port RAM -- Xilinx HDL Language Template version 8.1i RAMB4_S16_S16_inst2A : RAMB4_S16_S16 port map ( DOA => open, -- Port A 16-bit data output DOB => DO2A, -- Port B 16-bit data output ADDRA => ADDR2w, -- Port A 8-bit address input ADDRB => ADDR2r, -- Port B 8-bit address input CLKA => clk, -- Port A clock input CLKB => clk, -- Port B clock input DIA => DI2A, -- Port A 16-bit data input DIB => (others=>'0'), -- Port B 16-bit data input ENA => '1', -- Port A RAM enable input ENB => '1', -- Port B RAM enable input RSTA => '0', -- Port A Synchronous reset input RSTB => '0', -- Port B Synchronous reset input WEA => '1', -- Port A RAM write enable input WEB => '0' -- Port B RAM write enable input ); -- End of RAMB4_S16_S16_inst2 instantiation end generate; end long_shiftreg_arch_VirtexE;