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From: cvs at opencores.org<cvs@o...>
Date: Wed Nov 29 13:08:37 CET 2006
Subject: [cvs-checkins] MODIFIED: CVSROOT ...
Date: 00/06/11 29:13:08 Added: CVSROOT/VHDL/Spartan3 long_shiftreg.vhd
Log:
Long shift register for VirtexE and Spartan3 added
The counters of RC5KeyBreaker were slightly modified because this last version was constraining the operating frequency
Revision Changes Path
1.1 CVSROOT/VHDL/Spartan3/long_shiftreg.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/Spartan3/long_shiftreg.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: long_shiftreg.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis
-- Create Date: 27/11/2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity long_shiftreg is
generic(
depthA : integer := 4; -- depth of shift register A (between 4 and 259)
depthB : integer := 4); -- depth of shift register B (between 4 and 259)
port(
clk : in std_logic;
A_in : in std_logic_vector (31 downto 0);
B_in : in std_logic_vector (31 downto 0);
A_out : out std_logic_vector (31 downto 0);
B_out : out std_logic_vector (31 downto 0));
end long_shiftreg;
architecture long_shiftreg_arch_Spartan3 of long_shiftreg is
constant n : integer := 32;
constant ShRegStyleThreshold : integer := 4;
component delay_shiftreg
generic(
n : integer;
delay : integer);
port(
clk : in std_logic;
sig_in : in std_logic_vector (n-1 downto 0);
sig_out : out std_logic_vector (n-1 downto 0));
end component;
begin
gen_smallShReg: if (depthA < ShRegStyleThreshold) or (depthB < ShRegStyleThreshold) generate
begin
ShRagA: delay_shiftreg generic map(n,depthA) port map(clk,A_in,A_out);
ShRagB: delay_shiftreg generic map(n,depthB) port map(clk,B_in,B_out);
end generate;
gen_bigShReg: if not((depthA < ShRegStyleThreshold) or (depthB < ShRegStyleThreshold)) generate
signal DOA,DOB,DIA,DIB : std_logic_vector(31 downto 0);
signal ADDRA,ADDRB : std_logic_vector(8 downto 0);
begin
DIA <= A_in;
DIB <= B_in;
A_out <= DOA;
B_out <= DOB;
gen_equal_depth: if (depthA = depthB) generate
signal ABcounter : std_logic_vector(8 downto 0):=(others=>'1');
begin
proc_countAB: process(clk)
begin
if rising_edge(clk) then
if (ABcounter(8) = '1') then -- if ABcounter < 0 (2's complement)
ABcounter <= CONV_STD_LOGIC_VECTOR(depthA - 3, 9); -- a -1 is added since the output of bRAM is registred
else
ABcounter <= ABcounter - 1;
end if;
end if;
end process;
ADDRA <= '0' & ABcounter(7 downto 0);
ADDRB <= '1' & ABcounter(7 downto 0);
end generate;
gen_notequal_depth: if not(depthA = depthB) generate
signal Acounter,Bcounter : std_logic_vector(8 downto 0):=(others=>'1');
begin
proc_countA: process(clk)
begin
if rising_edge(clk) then
if (Acounter(8) = '1') then -- if ABcounter < 0 (2's complement)
Acounter <= CONV_STD_LOGIC_VECTOR(depthA - 3, 9);
else
Acounter <= Acounter - 1;
end if;
end if;
end process;
proc_countB: process(clk)
begin
if rising_edge(clk) then
if (Bcounter(8) = '1') then -- if ABcounter < 0 (2's complement)
Bcounter <= CONV_STD_LOGIC_VECTOR(depthB - 3, 9);
else
Bcounter <= Bcounter - 1;
end if;
end if;
end process;
ADDRA <= '0' & Acounter(7 downto 0);
ADDRB <= '1' & Bcounter(7 downto 0);
end generate;
-- RAMB16_S36_S36: Virtex-II/II-Pro, Spartan-3/3E 512 x 32 + 4 Parity bits Dual-Port RAM
-- Xilinx HDL Language Template version 8.1i
RAMB16_S36_S36_inst : RAMB16_S36_S36
generic map (
INIT_A => X"000000000", -- Value of output RAM registers on Port A at startup
INIT_B => X"000000000", -- Value of output RAM registers on Port B at startup
SRVAL_A => X"000000000", -- Port A ouput value upon SSR assertion
SRVAL_B => X"000000000", -- Port B ouput value upon SSR assertion
WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
SIM_COLLISION_CHECK => "ALL" -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL
)
port map (
DOA => DOA, -- Port A 32-bit Data Output
DOB => DOB, -- Port B 32-bit Data Output
DOPA => open, -- Port A 4-bit Parity Output
DOPB => open, -- Port B 4-bit Parity Output
ADDRA => ADDRA, -- Port A 9-bit Address Input
ADDRB => ADDRB, -- Port B 9-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => DIA, -- Port A 32-bit Data Input
DIB => DIB, -- Port B 32-bit Data Input
DIPA => (others=>'0'), -- Port A 4-bit parity Input
DIPB => (others=>'0'), -- Port-B 4-bit parity Input
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- Port B RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => '1', -- Port A Write Enable Input
WEB => '1' -- Port B Write Enable Input
);
-- End of RAMB16_S36_S36_inst instantiation
end generate;
end long_shiftreg_arch_Spartan3;
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