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From: cvs at opencores.org<cvs@o...>
Date: Wed Nov 29 13:08:36 CET 2006
Subject: [cvs-checkins] MODIFIED: CVSROOT ...
Date: 00/06/11 29:13:08

Modified: CVSROOT/VHDL/testing RC5KeyBreaker.vhd
Log:
Long shift register for VirtexE and Spartan3 added



The counters of RC5KeyBreaker were slightly modified because this last version was constraining the operating frequency


Revision Changes Path
1.2 CVSROOT/VHDL/testing/RC5KeyBreaker.vhd

http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/RC5KeyBreaker.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: RC5KeyBreaker.vhd
===================================================================
RCS file: /cvsroot/gmeurice/CVSROOT/VHDL/testing/RC5KeyBreaker.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- RC5KeyBreaker.vhd 28 Nov 2006 00:41:41 -0000 1.1
+++ RC5KeyBreaker.vhd 29 Nov 2006 12:08:36 -0000 1.2
@@ -12,6 +12,7 @@
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
@@ -30,18 +31,23 @@

architecture RC5KeyBreaker_arch of RC5KeyBreaker is

+--attribute SHREG_EXTRACT: string;
+--attribute SHREG_EXTRACT of RC5KeyBreaker_arch: architecture is "no";
+
signal Ptxt : std_logic_vector(2*n-1 downto 0) := To_StdLogicVector(Plaintext_contest);
signal ok_P,ok_Q : std_logic;
signal go,go_reg,yeah,yeah_reg : std_logic;
signal key_counter,key_counter_reg : std_logic_vector(n-1 downto 0);

-signal counter_main : std_logic_vector(n downto 0) := "100000000000000000000000000000001";
+signal counter_main : std_logic_vector(n downto 0) := "100000000000000000000000000000000";
signal counter_mirror : std_logic_vector(n-1 downto 0) := x"00000000";
signal delay_counter : std_logic_vector(9 downto 0) := "0000000000"; -- depends on the size of "total_delay"

signal key : std_logic_vector(3*n-1 downto 0);
signal key_range_effective,key_range,key_range_reg : std_logic_vector (39 downto 0);

+signal counter_main_sign : std_logic;
+
type state_type is (S1,S2);
signal state : state_type := S1;

@@ -72,6 +78,8 @@
key_counter_reg <= key_counter;
key_counter_out <= key_counter_reg;

+ counter_main_sign <= counter_main(32);
+
if yeah = '1' then
key_counter <= counter_mirror;
end if;
@@ -86,11 +94,11 @@
count_proc: process(clk)
begin
if rising_edge(clk) then
- if counter_main(32) = '1' then
- delay_counter <= CONV_STD_LOGIC_VECTOR(total_delay -4 + 2 +1, 10); -- +2 comes from the addition of 2 registers for testing the output. +1 because there is a difference of 1 between the init of the two counters
+ if counter_main_sign = '1' then
+ delay_counter <= CONV_STD_LOGIC_VECTOR(total_delay -4 + 2, 10); -- +2 comes from the addition of 2 registers for testing the output.
if go = '1' then
key_range_effective <= key_range;
- counter_main <= CONV_STD_LOGIC_VECTOR(1 + 1392705536, 33);
+ counter_main <= CONV_STD_LOGIC_VECTOR(2 + 1392705536, 33);
-- else
-- wait for the new key_range
-- no counter increment
@@ -112,14 +120,14 @@
when S1 => -- Wait and Load phase 1
if (delay_counter(9) = '1') then
state <= S2;
- counter_mirror <= CONV_STD_LOGIC_VECTOR(0+ 1392705536, 32);
+ counter_mirror <= CONV_STD_LOGIC_VECTOR(0 + 1392705536, 32);
else
state <= S1;
counter_mirror <= counter_mirror + 1;
end if;
when S2 => -- Load phase 2
counter_mirror <= counter_mirror + 1;
- if (counter_main(32) = '1') then
+ if (counter_main_sign = '1') then
state <= S1;
else
state <= S2;