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Message
From: cvs at opencores.org<cvs@o...>
Date: Tue Nov 28 01:41:42 CET 2006
Subject: [cvs-checkins] MODIFIED: CVSROOT ...
Date: 00/06/11 28:01:41 Added: CVSROOT/VHDL/testing RC5KeyBreaker.vhd RC5_test.py
TB1_RC5encrypt.vhd TB2_RC5encrypt.vhd
TB_EncryptBloc.vhd TB_KeyScheduleBloc.vhd
TB_RC5KeyBreaker.vhd TB_long_shiftreg.vhd
TB_rotate_shiftreg.vhd cstPack.vhd
Log:
Here it is (at last).
In the folder "shared_files" are the files used for most of the configurations
Specific files for specific platforms lies in other folders.
The folder "testing" embed the test benches as well as a python script used to generate test data files (and to help generating code for TB.vhd files).
Using_LbRAMs replace regular shift register by shift registers based on bRAMs.
Currently, the real difference between platforms is the way "long_shiftReg" is implemented (because bRAMS instanciation is different).
Enjoy!
--
Guerric
Revision Changes Path
1.1 CVSROOT/VHDL/testing/RC5KeyBreaker.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/RC5KeyBreaker.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: RC5KeyBreaker.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis
-- Create Date: 7/11/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use WORK.cstPack.all;
use WORK.compoPack.all;
entity RC5KeyBreaker is
port( -- it is assumed that the user can store the previous key_range. As a result, only the counter is provided when the key matches
clk, go_in : in std_logic;
key_range_in : in std_logic_vector (39 downto 0);
yeah_out : out std_logic;
key_counter_out : out std_logic_vector (n-1 downto 0));
end RC5KeyBreaker;
architecture RC5KeyBreaker_arch of RC5KeyBreaker is
signal Ptxt : std_logic_vector(2*n-1 downto 0) := To_StdLogicVector(Plaintext_contest);
signal ok_P,ok_Q : std_logic;
signal go,go_reg,yeah,yeah_reg : std_logic;
signal key_counter,key_counter_reg : std_logic_vector(n-1 downto 0);
signal counter_main : std_logic_vector(n downto 0) := "100000000000000000000000000000001";
signal counter_mirror : std_logic_vector(n-1 downto 0) := x"00000000";
signal delay_counter : std_logic_vector(9 downto 0) := "0000000000"; -- depends on the size of "total_delay"
signal key : std_logic_vector(3*n-1 downto 0);
signal key_range_effective,key_range,key_range_reg : std_logic_vector (39 downto 0);
type state_type is (S1,S2);
signal state : state_type := S1;
begin
RC5_compo: RC5encrypt port map(clk,key,Ptxt,ok_P,ok_Q);
finding_proc: process(clk)
begin
if rising_edge(clk) then
if (ok_P = '1') and (ok_Q = '1') then
yeah <= '1';
else
yeah <= '0';
end if;
end if;
end process;
reg_proc: process(clk)
begin
if rising_edge(clk) then
go_reg <= go_in;
go <= go_reg;
key_range_reg <= key_range_in;
key_range <= key_range_reg;
yeah_reg <= yeah;
yeah_out <= yeah_reg;
key_counter_reg <= key_counter;
key_counter_out <= key_counter_reg;
if yeah = '1' then
key_counter <= counter_mirror;
end if;
end if;
end process;
-- Probably not yet compatible with distributed.net concerning the way to increment the counter
-- there is 2 counters. The main and a mirror with an offset of the total delay of the pipeline
count_proc: process(clk)
begin
if rising_edge(clk) then
if counter_main(32) = '1' then
delay_counter <= CONV_STD_LOGIC_VECTOR(total_delay -4 + 2 +1, 10); -- +2 comes from the addition of 2 registers for testing the output. +1 because there is a difference of 1 between the init of the two counters
if go = '1' then
key_range_effective <= key_range;
counter_main <= CONV_STD_LOGIC_VECTOR(1 + 1392705536, 33);
-- else
-- wait for the new key_range
-- no counter increment
end if;
else
counter_main <= counter_main + 1;
if delay_counter(9) = '0' then -- not mandatory
delay_counter <= delay_counter -1;
end if;
end if;
end if;
end process;
mirror_count_process : process(clk)
begin
if rising_edge(clk) then
case state is
when S1 => -- Wait and Load phase 1
if (delay_counter(9) = '1') then
state <= S2;
counter_mirror <= CONV_STD_LOGIC_VECTOR(0+ 1392705536, 32);
else
state <= S1;
counter_mirror <= counter_mirror + 1;
end if;
when S2 => -- Load phase 2
counter_mirror <= counter_mirror + 1;
if (counter_main(32) = '1') then
state <= S1;
else
state <= S2;
end if;
end case;
end if;
end process;
key <= x"000000" & key_range_effective & counter_main(n-1 downto 0);
end RC5KeyBreaker_arch;
1.1 CVSROOT/VHDL/testing/RC5_test.py
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/RC5_test.py?rev=1.1&content-type=text/x-cvsweb-markup
Index: RC5_test.py
===================================================================
#################################################################################
## Univeriste catholique de Louvain
## UCL DICE/Crypto Group
## Place du Levant, 3
## B-1348 Louvain-la-Neuve
## Belgium
##
## Guerric Meurice de Dormale
## Create Date: 19/10/2006
#################################################################################
#This may freely be used, as long as copyright notices are maintained per BSD licensing
#Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
#################################################################################
import random
def dec2bin(nbr):
bin_nbr = ''
if (nbr == 0):
return '0'
while nbr != 0:
bin_nbr = str(nbr & 1) + bin_nbr
nbr = nbr >> 1
return bin_nbr
def write_vhdl_retrieve_data(l):
str_vhdl = ''
str_vhdl += 'Data_input : process\n'
str_tmp = ''
for i in range(len(l)):
for el in l[i][0]:
str_tmp += el + '_file,'
str_vhdl += ' file ' + str_tmp[0:-1] + ' : text;\n' ## str_tmp without the last coma
str_vhdl += ' variable INline: line;\n'
for i in range(len(l)):
bit_range = l[i][1]
str_tmp = ' variable INdata_'
str_tmp += bit_range
if bit_range == '1':
str_tmp += ': bit;\n'
else:
str_tmp += ' : bit_vector(' + bit_range + '-1 downto 0);\n'
str_vhdl += str_tmp
for i in range(len(l)):
str_tmp = ' variable '
for el in l[i][0]:
str_tmp += el + '_tmp,'
str_tmp = str_tmp[0:-1]
bit_range = l[i][1]
if bit_range == '1':
str_tmp += ' : std_logic;\n'
else:
str_tmp += ' : std_logic_vector(' + bit_range + '-1 downto 0);\n'
str_vhdl += str_tmp
str_vhdl += '\n'
str_vhdl += 'begin\n'
for i in range(len(l)):
for el in l[i][0]:
str_tmp = ' file_open(' + el + '_file,"TB_'
if el[0:3] == 'Res':
str_tmp += el
else:
str_tmp += 'Operand' + el
str_tmp += '.tb",read_mode);\n'
str_vhdl += str_tmp
str_vhdl += ' while true loop\n'
str_vhdl += ' wait until rising_edge(clk);\n'
str_vhdl += ' if not(endfile(' + l[0][0][0] + '_file)) then\n'
for i in range(len(l)):
bit_range = l[i][1]
for el in l[i][0]:
str_tmp = ' readline(' + el + '_file,INline);\n'
str_tmp += ' read(INline,INdata_' + bit_range + ');\n'
str_tmp += ' ' + el + '_tmp := '
if bit_range == '1':
str_tmp += 'To_StdULogic('
else:
str_tmp += 'To_StdLogicVector('
str_tmp += 'INdata_' + bit_range + ');\n'
str_vhdl += str_tmp
str_vhdl += '\n'
str_vhdl += ' wait for 1 ns;\n\n'
for i in range(len(l)):
for el in l[i][0]:
str_vhdl += ' ' + el + ' <= ' + el + '_tmp;\n'
str_vhdl += ' end if;\n'
str_vhdl += ' end loop;\n'
str_vhdl += 'end process;\n'
return str_vhdl
def rotate(A,rot,A_size):
rot = rot & (A_size - 1)
return ((A << rot) % 2**A_size) | (A >> (A_size - rot))
def rotate_test(nbr_iter):
n = 32
rot_size = 4
rot_size_default = 5
fileX = open("TB_OperandX.tb",'w')
fileY = open("TB_OperandY.tb",'w')
fileRes = open("TB_Res.tb",'w')
l_retrieve_data = [(['X','Res'],'n'),(['Y'],'rot_size')]
for i in xrange(nbr_iter):
X = random.getrandbits(n)
Y = random.getrandbits(rot_size)
result = rotate(X,Y,n)
X_str = dec2bin(X)
Y_str = dec2bin(Y)
result_str = dec2bin(result)
fileX.write(X_str.zfill(n)+'\n')
fileY.write(Y_str.zfill(rot_size_default)+'\n')
fileRes.write(result_str.zfill(n)+'\n')
print write_vhdl_retrieve_data(l_retrieve_data)
fileX.close()
fileY.close()
fileRes.close()
return
def shiftreg_test(nbr_iter):
n = 32
fileA = open("TB_OperandA.tb",'w')
fileB = open("TB_OperandB.tb",'w')
l_retrieve_data = [(['A','B'],'n')]
for i in range(nbr_iter):
A = random.getrandbits(n)
B = random.getrandbits(n)
A_str = dec2bin(A)
B_str = dec2bin(B)
fileA.write(A_str.zfill(n)+'\n')
fileB.write(B_str.zfill(n)+'\n')
print write_vhdl_retrieve_data(l_retrieve_data)
fileA.close()
fileB.close()
return
def KeyScheduleBloc(A_in,S_in,B_in,L_in,B_in_rot_cmd,L_in_rot_cmd,do_complete_rotate,n):
A_out_tmp = (A_in + S_in + rotate(B_in,B_in_rot_cmd*16,n)) % 2**n
A_out = rotate(A_out_tmp,3,n)
rot_in_tmp1 = (A_out + rotate(B_in,B_in_rot_cmd*16,n)) % 2**n
if do_complete_rotate:
rot_cmd = rot_in_tmp1 % 2**5
else:
rot_cmd = rot_in_tmp1 % 2**4
rot_in_tmp2 = (rot_in_tmp1 + rotate(L_in,L_in_rot_cmd*16,n)) % 2**n
B_out = rotate(rot_in_tmp2,rot_cmd,n)
return [A_out,B_out]
def keySchedule_test(nbr_iter):
n = 32
do_complete_rotate = False
fileA = open("TB_OperandA.tb",'w')
fileB = open("TB_OperandB.tb",'w')
fileB_cmd = open("TB_OperandB_cmd.tb",'w')
fileS = open("TB_OperandS.tb",'w')
fileL = open("TB_OperandL.tb",'w')
fileL_cmd = open("TB_OperandL_cmd.tb",'w')
fileResA = open("TB_ResA.tb",'w')
fileResB = open("TB_ResB.tb",'w')
l_retrieve_data = [(['A','B','S','L','ResA','ResB'],'n'),(['B_cmd','L_cmd'],'1')]
B_str = str(0)
B_cmd_str = str(0)
L_str = str(0)
L_cmd_str = str(0)
fileB.write(B_str.zfill(n)+'\n')
fileB_cmd.write(B_cmd_str+'\n')
for i in range(3):
fileL.write(L_str.zfill(n)+'\n')
fileL_cmd.write(L_cmd_str+'\n')
for i in xrange(nbr_iter):
A = random.getrandbits(n)
B = random.getrandbits(n)
B_cmd = random.getrandbits(1)
S = random.getrandbits(n)
L = random.getrandbits(n)
L_cmd = random.getrandbits(1)
[ResA,ResB] = KeyScheduleBloc(A,S,B,L,B_cmd,L_cmd,do_complete_rotate,n)
A_str = dec2bin(A)
B_str = dec2bin(B)
B_cmd_str = str(B_cmd)
S_str = dec2bin(S)
L_str = dec2bin(L)
L_cmd_str = str(L_cmd)
ResA_str = dec2bin(ResA)
ResB_str = dec2bin(ResB)
fileA.write(A_str.zfill(n)+'\n')
fileB.write(B_str.zfill(n)+'\n')
fileB_cmd.write(B_cmd_str+'\n')
fileS.write(S_str.zfill(n)+'\n')
fileL.write(L_str.zfill(n)+'\n')
fileL_cmd.write(L_cmd_str+'\n')
fileResA.write(ResA_str.zfill(n)+'\n')
fileResB.write(ResB_str.zfill(n)+'\n')
print write_vhdl_retrieve_data(l_retrieve_data)
fileA.close()
fileB.close()
fileB_cmd.close()
fileS.close()
fileL.close()
fileL_cmd.close()
fileResA.close()
fileResB.close()
return
def EncryptBloc(P,Q,S1,S2,do_complete_rotate,n):
PQxor1 = P ^ Q
if do_complete_rotate:
rot_cmd1 = Q % 2**5
else:
rot_cmd1 = Q % 2**4
rot_cmd1_MSB = Q & 2**4 # cmd bits for shift16 (16 or not)
rot_out1 = rotate(PQxor1,rot_cmd1,n)
P = (S1 + rotate(rot_out1,rot_cmd1_MSB,n)) % 2**n
PQxor2 = P ^ Q
if do_complete_rotate:
rot_cmd2 = P % 2**5
else:
rot_cmd2 = P % 2**4
rot_cmd2_MSB = P & 2**4 # cmd bits for shift16 (16 or not)
rot_out2 = rotate(PQxor2,rot_cmd2,n)
Q = (S2 + rotate(rot_out2,rot_cmd2_MSB,n)) % 2**n
return [P,Q]
def EncryptBloc_test(nbr_iter):
n = 32
do_complete_rotate = False
file_P = open("TB_OperandP.tb",'w')
file_Q = open("TB_OperandQ.tb",'w')
file_S1 = open("TB_OperandS1.tb",'w')
file_S2 = open("TB_OperandS2.tb",'w')
file_ResP = open("TB_ResP.tb",'w')
file_ResQ = open("TB_ResQ.tb",'w')
l_retrieve_data = [(['P','Q','S1','S2','ResP','ResQ'],'n')]
S1_str = str(0)
S2_str = str(0)
for i in range(4):
file_S1.write(S1_str.zfill(n)+'\n')
for i in range(9):
file_S2.write(S1_str.zfill(n)+'\n')
for i in xrange(nbr_iter):
P = random.getrandbits(n)
Q = random.getrandbits(n)
S1 = random.getrandbits(n)
S2 = random.getrandbits(n)
[ResP,ResQ] = EncryptBloc(P,Q,S1,S2,do_complete_rotate,n)
P_str = dec2bin(P)
Q_str = dec2bin(Q)
S1_str = dec2bin(S1)
S2_str = dec2bin(S2)
ResP_str = dec2bin(ResP)
ResQ_str = dec2bin(ResQ)
file_P.write(P_str.zfill(n)+'\n')
file_Q.write(Q_str.zfill(n)+'\n')
file_S1.write(S1_str.zfill(n)+'\n')
file_S2.write(S2_str.zfill(n)+'\n')
file_ResP.write(ResP_str.zfill(n)+'\n')
file_ResQ.write(ResQ_str.zfill(n)+'\n')
print write_vhdl_retrieve_data(l_retrieve_data)
file_P.close()
file_Q.close()
file_S1.close()
file_S2.close()
file_ResP.close()
file_ResQ.close()
return
def RC5encrypt(key,Ptxt):
w = 32
r = 12
#b = 9
t = 2*(r+1)
c = 3
S32 = 0xB7E15163
T32 = 0x9E3779B9
# init L
L = []
for i in range(c):
L.append(key % 2**w)
key = key >> w
## the MSBs must be in L[2]
# init S
S = []
S.append(S32)
for i in range(t-1):
S.append( (S[i]+T32)% 2**w )
# key sched
A = 0
B = 0
i = 0
j = 0
for k_index in range(3*max(t,c)):
A = (S[i] + A + B) % 2**w
A = rotate(A,3,w)
S[i] = A
rot_cmd = (A+B) % 2**5
B = (L[j] + A + B) % 2**w
B = rotate(B,rot_cmd,w)
L[j] = B
i = (i+1) % t
j = (j+1) % c
# init P,Q
P = Ptxt % 2**w
Q = (Ptxt >> w) % 2**w ## MSBs must be in Q
# encrypt
P = (P + S[0]) % 2**w
Q = (Q + S[1]) % 2**w
for i in range(1,r+1):
P = ( rotate(P^Q,Q,w) + S[2*i] ) % 2**w
Q = ( rotate(Q^P,P,w) + S[2*i+1] ) % 2**w
result = (Q << w) | P
return result
def RC5encrypt_test1(nbr_iter):
#Key: c9 0c 03 53 c0 d4 e1 fe 85
key = 0x85fee1d4c053030cc9
#IV: 07 ce 59 1f 86 14 9a 41
IV = 0x419a14861f59ce07
#"The unkn": 54 68 65 20 75 6e 6b 6e
Ptxt = 0x6e6b6e7520656854
#Ciphertext: 5a 28 2d 56 2a 85 b7 2f
Ctxt = 0x2fb7852a562d285a
res = RC5encrypt(key,Ptxt^IV)
if res != Ctxt:
print "!!!!!!!!!!boulet"
print hex(res)
print hex(Ctxt)
else:
print "perfecto"
return
def RC5encrypt_test2(nbr_iter):
n = 32
do_complete_rotate = False
file_Ptxt = open("TB_OperandPtxt.tb",'w')
file_Key = open("TB_OperandKey.tb",'w')
file_Res = open("TB_Res.tb",'w')
l_retrieve_data = [(['Ptxt','Res'],'2*n'),(['Key'],'3*n')]
for i in xrange(nbr_iter):
Ptxt = random.getrandbits(2*n)
Key = random.getrandbits(2*n+8)
Res = RC5encrypt(Key,Ptxt)
Ptxt_str = dec2bin(Ptxt)
Key_str = dec2bin(Key)
Res_str = dec2bin(Res)
file_Ptxt.write(Ptxt_str.zfill(2*n)+'\n')
file_Key.write(Key_str.zfill(3*n)+'\n')
file_Res.write(Res_str.zfill(2*n)+'\n')
print write_vhdl_retrieve_data(l_retrieve_data)
file_Ptxt.close()
file_Key.close()
file_Res.close()
return
#--------------------
# process fonctions
print "begin"
#rotate_test(1000)
#shiftreg_test(10000)
#keySchedule_test(1000)
#EncryptBloc_test(10000)
#RC5encrypt_test1(1)
RC5encrypt_test2(1000000)
print "end"
1.1 CVSROOT/VHDL/testing/TB1_RC5encrypt.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/TB1_RC5encrypt.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: TB1_RC5encrypt.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Create Date: 30/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_arith.all;
use WORK.cstPack.all;
entity TB1_RC5encrypt is
end TB1_RC5encrypt;
architecture behavior of TB1_RC5encrypt is
-- Component Declaration
component RC5encrypt
port(
clk : in std_logic;
key : in std_logic_vector (3*n-1 downto 0);
Plaintext : in std_logic_vector(2*n-1 downto 0);
Ciphertext : out std_logic_vector (2*n-1 downto 0));
end component;
constant delayPQ : integer := 10;
--Inputs
signal clk : std_logic := '0';
signal key : std_logic_vector(3*n-1 downto 0) := x"00000085fee1d4c053030cc9";
signal Plaintext : std_logic_vector(2*n-1 downto 0) := x"6e6b6e7520656854";
signal IV : std_logic_vector(2*n-1 downto 0) := x"419a14861f59ce07";
signal Plaintext_IV : std_logic_vector(2*n-1 downto 0);
--signal key_bv : bit_vector;
--signal Plaintext_bv : bit_vector;
--signal IV_bv : bit_vector;
--Outputs
signal Ciphertext : std_logic_vector(2*n-1 downto 0);
--User Defined
constant half_clk_prd : time := 2.5 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: RC5encrypt port map(clk,key,Plaintext_IV,Ciphertext);
Plaintext_IV <= Plaintext xor IV;
clk <= not(clk) after half_clk_prd;
end;
1.1 CVSROOT/VHDL/testing/TB2_RC5encrypt.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/TB2_RC5encrypt.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: TB2_RC5encrypt.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Create Date: 30/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_arith.all;
use WORK.cstPack.all;
entity TB2_RC5encrypt is
end TB2_RC5encrypt;
architecture behavior of TB2_RC5encrypt is
-- Component Declaration
component RC5encrypt
port(
clk : in std_logic;
key : in std_logic_vector (3*n-1 downto 0);
Plaintext : in std_logic_vector(2*n-1 downto 0);
Ciphertext : out std_logic_vector (2*n-1 downto 0));
end component;
constant n : integer := 32;
constant delay : integer := total_delay;
constant delay_in : integer := in_Ptxt_delay;
--Inputs
signal clk : std_logic := '0';
signal key : std_logic_vector(3*n-1 downto 0) := (others=>'0');
signal Plaintext : std_logic_vector(2*n-1 downto 0) := (others=>'0');
--Outputs
signal Ciphertext : std_logic_vector (2*n-1 downto 0);
--User Defined
signal ok : std_logic;
constant half_clk_prd : time := 2.5 ns;
signal Res,Res_delayed,in_Ptxt_delayed : std_logic_vector(2*n-1 downto 0);
type delay_array_type is array (delay-1 downto 0) of std_logic_vector(2*n-1 downto 0);
signal delay_arrayRes : delay_array_type;
type delay_array_type2 is array (delay_in-1 downto 0) of std_logic_vector(2*n-1 downto 0);
signal delay_arrayin_Ptxt : delay_array_type2;
begin
-- Instantiate the Unit Under Test (UUT)
uut: RC5encrypt port map(clk,key,in_Ptxt_delayed,Ciphertext);
clk <= not(clk) after half_clk_prd;
check_proc : process(clk)
begin
if rising_edge(clk) then
if (Res_delayed = Ciphertext) then
ok <= '1';
else
ok <= '0';
end if;
end if;
end process;
delay_shift_proc : process(clk)
begin
if rising_edge(clk) then
delay_arrayRes <= Res & delay_arrayRes(delay-1 downto 1);
delay_arrayin_Ptxt <= Plaintext & delay_arrayin_Ptxt(delay_in-1 downto 1);
end if;
end process;
Res_delayed <= delay_arrayRes(0);
in_Ptxt_delayed <= delay_arrayin_Ptxt(0);
Data_input : process
file Ptxt_file,Res_file,Key_file : text;
variable INline: line;
variable INdata_2n : bit_vector(2*n-1 downto 0);
variable INdata_3n : bit_vector(3*n-1 downto 0);
variable Ptxt_tmp,Res_tmp : std_logic_vector(2*n-1 downto 0);
variable Key_tmp : std_logic_vector(3*n-1 downto 0);
begin
file_open(Ptxt_file,"TB_OperandPtxt.tb",read_mode);
file_open(Res_file,"TB_Res.tb",read_mode);
file_open(Key_file,"TB_OperandKey.tb",read_mode);
while true loop
wait until rising_edge(clk);
if not(endfile(Ptxt_file)) then
readline(Ptxt_file,INline);
read(INline,INdata_2n);
Ptxt_tmp := To_StdLogicVector(INdata_2n);
readline(Res_file,INline);
read(INline,INdata_2n);
Res_tmp := To_StdLogicVector(INdata_2n);
readline(Key_file,INline);
read(INline,INdata_3n);
Key_tmp := To_StdLogicVector(INdata_3n);
wait for 1 ns;
Plaintext <= Ptxt_tmp;
Res <= Res_tmp;
key <= Key_tmp;
end if;
end loop;
end process;
end;
1.1 CVSROOT/VHDL/testing/TB_EncryptBloc.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/TB_EncryptBloc.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: TB_EncryptBloc.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Create Date: 30/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_arith.all;
use WORK.cstPack.all;
entity TB_EncryptBloc is
end TB_EncryptBloc;
architecture behavior of TB_EncryptBloc is
-- Component Declaration
component EncryptBloc
port(
clk : in std_logic;
P_in,Q_in,S1,S2 : in std_logic_vector (31 downto 0);
P_out,Q_out : out std_logic_vector (31 downto 0));
end component;
constant n : integer := 32;
constant delayPQ : integer := 10;
--Inputs
signal clk : std_logic := '0';
signal P_in,Q_in,S1,S2 : std_logic_vector(n-1 downto 0) := (others=>'0');
--Outputs
signal P_out,Q_out : std_logic_vector(n-1 downto 0);
--User Defined
signal ok : std_logic;
constant half_clk_prd : time := 2.5 ns;
signal ResP,ResP_delayed,ResQ,ResQ_delayed : std_logic_vector(n-1 downto 0);
type delay_array_type is array (delayPQ-1 downto 0) of std_logic_vector(n-1 downto 0);
signal delay_arrayResP,delay_arrayResQ : delay_array_type;
begin
-- Instantiate the Unit Under Test (UUT)
uut: EncryptBloc port map(clk,P_in,Q_in,S1,S2,P_out,Q_out);
clk <= not(clk) after half_clk_prd;
check_proc : process(clk)
begin
if rising_edge(clk) then
if (ResP_delayed = P_out) and (ResQ_delayed = Q_out) then
ok <= '1';
else
ok <= '0';
end if;
end if;
end process;
delay_shift_proc : process(clk)
begin
if rising_edge(clk) then
delay_arrayResP <= ResP & delay_arrayResP(delayPQ-1 downto 1);
delay_arrayResQ <= ResQ & delay_arrayResQ(delayPQ-1 downto 1);
end if;
end process;
ResP_delayed <= delay_arrayResP(0);
ResQ_delayed <= delay_arrayResQ(0);
Data_input : process
file P_file,Q_file,S1_file,S2_file,ResP_file,ResQ_file : text;
variable INline: line;
variable INdata_n : bit_vector(n-1 downto 0);
variable P_tmp,Q_tmp,S1_tmp,S2_tmp,ResP_tmp,ResQ_tmp : std_logic_vector(n-1 downto 0);
begin
file_open(P_file,"TB_OperandP.tb",read_mode);
file_open(Q_file,"TB_OperandQ.tb",read_mode);
file_open(S1_file,"TB_OperandS1.tb",read_mode);
file_open(S2_file,"TB_OperandS2.tb",read_mode);
file_open(ResP_file,"TB_ResP.tb",read_mode);
file_open(ResQ_file,"TB_ResQ.tb",read_mode);
while true loop
wait until rising_edge(clk);
if not(endfile(P_file)) then
readline(P_file,INline);
read(INline,INdata_n);
P_tmp := To_StdLogicVector(INdata_n);
readline(Q_file,INline);
read(INline,INdata_n);
Q_tmp := To_StdLogicVector(INdata_n);
readline(S1_file,INline);
read(INline,INdata_n);
S1_tmp := To_StdLogicVector(INdata_n);
readline(S2_file,INline);
read(INline,INdata_n);
S2_tmp := To_StdLogicVector(INdata_n);
readline(ResP_file,INline);
read(INline,INdata_n);
ResP_tmp := To_StdLogicVector(INdata_n);
readline(ResQ_file,INline);
read(INline,INdata_n);
ResQ_tmp := To_StdLogicVector(INdata_n);
wait for 1 ns;
P_in <= P_tmp;
Q_in <= Q_tmp;
S1 <= S1_tmp;
S2 <= S2_tmp;
ResP <= ResP_tmp;
ResQ <= ResQ_tmp;
end if;
end loop;
end process;
end;
1.1 CVSROOT/VHDL/testing/TB_KeyScheduleBloc.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/TB_KeyScheduleBloc.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: TB_KeyScheduleBloc.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Create Date: 19/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_arith.all;
entity TB_KeyScheduleBloc is
end TB_KeyScheduleBloc;
architecture behavior of TB_KeyScheduleBloc is
-- Component Declaration
component KeyScheduleBloc
generic(
delay_Asig : integer := 3;
delay_Brot_cmd : integer := 3;
delay_Lout_cmd : integer := 14;
delay_Lout : integer := 12);
port(
clk : in std_logic;
A_in,S_in,B_in,L_in : in std_logic_vector (31 downto 0);
B_in_rot_cmd,L_in_rot_cmd : in std_logic;
A_out,S_out,B_out,L_out : out std_logic_vector (31 downto 0);
B_out_rot_cmd,L_out_rot_cmd : out std_logic);
end component;
constant n : integer := 32;
constant delayA : integer := 5; -- et pas 2 car shift reg sur A_out aussi (de 3)
constant delayB : integer := 6;
--Inputs
signal clk : std_logic := '0';
signal A_in,S_in,B_in,L_in : std_logic_vector(n-1 downto 0) := (others=>'0');
signal B_in_rot_cmd,L_in_rot_cmd : std_logic := '0';
--Outputs
signal A_out,S_out,B_out,L_out : std_logic_vector(n-1 downto 0);
signal B_out_rot_cmd,L_out_rot_cmd : std_logic;
--User Defined
signal ok : std_logic;
constant half_clk_prd : time := 2.5 ns;
signal ResA,ResA_delayed,ResB,ResB_delayed : std_logic_vector(n-1 downto 0);
type delay_array_typeA is array (delayA-1 downto 0) of std_logic_vector(n-1 downto 0);
signal delay_arrayResA : delay_array_typeA;
type delay_array_typeB is array (delayB-1 downto 0) of std_logic_vector(n-1 downto 0);
signal delay_arrayResB : delay_array_typeB;
begin
-- Instantiate the Unit Under Test (UUT)
uut: KeyScheduleBloc port map(clk,A_in,S_in,B_in,L_in,B_in_rot_cmd,L_in_rot_cmd,A_out,S_out,B_out,L_out,B_out_rot_cmd,L_out_rot_cmd);
clk <= not(clk) after half_clk_prd;
check_proc : process(clk)
begin
if rising_edge(clk) then
if (ResA_delayed = A_out) and (ResB_delayed = B_out) then
ok <= '1';
else
ok <= '0';
end if;
end if;
end process;
delay_shift_proc : process(clk)
begin
if rising_edge(clk) then
delay_arrayResA <= ResA & delay_arrayResA(delayA-1 downto 1);
delay_arrayResB <= ResB & delay_arrayResB(delayB-1 downto 1);
end if;
end process;
ResA_delayed <= delay_arrayResA(0);
ResB_delayed <= delay_arrayResB(0);
Data_input : process
file A_file,B_file,S_file,L_file,ResA_file,ResB_file,B_cmd_file,L_cmd_file : text;
variable INline: line;
variable INdata_n : bit_vector(n-1 downto 0);
variable INdata_1: bit;
variable A_tmp,B_tmp,S_tmp,L_tmp,ResA_tmp,ResB_tmp : std_logic_vector(n-1 downto 0);
variable B_cmd_tmp,L_cmd_tmp : std_logic;
begin
file_open(A_file,"TB_OperandA.tb",read_mode);
file_open(B_file,"TB_OperandB.tb",read_mode);
file_open(S_file,"TB_OperandS.tb",read_mode);
file_open(L_file,"TB_OperandL.tb",read_mode);
file_open(ResA_file,"TB_ResA.tb",read_mode);
file_open(ResB_file,"TB_ResB.tb",read_mode);
file_open(B_cmd_file,"TB_OperandB_cmd.tb",read_mode);
file_open(L_cmd_file,"TB_OperandL_cmd.tb",read_mode);
while true loop
wait until rising_edge(clk);
if not(endfile(A_file)) then
readline(A_file,INline);
read(INline,INdata_n);
A_tmp := To_StdLogicVector(INdata_n);
readline(B_file,INline);
read(INline,INdata_n);
B_tmp := To_StdLogicVector(INdata_n);
readline(S_file,INline);
read(INline,INdata_n);
S_tmp := To_StdLogicVector(INdata_n);
readline(L_file,INline);
read(INline,INdata_n);
L_tmp := To_StdLogicVector(INdata_n);
readline(ResA_file,INline);
read(INline,INdata_n);
ResA_tmp := To_StdLogicVector(INdata_n);
readline(ResB_file,INline);
read(INline,INdata_n);
ResB_tmp := To_StdLogicVector(INdata_n);
readline(B_cmd_file,INline);
read(INline,INdata_1);
B_cmd_tmp := To_StdULogic(INdata_1);
readline(L_cmd_file,INline);
read(INline,INdata_1);
L_cmd_tmp := To_StdULogic(INdata_1);
wait for 1 ns;
A_in <= A_tmp;
B_in <= B_tmp;
S_in <= S_tmp;
L_in <= L_tmp;
ResA <= ResA_tmp;
ResB <= ResB_tmp;
B_in_rot_cmd <= B_cmd_tmp;
L_in_rot_cmd <= L_cmd_tmp;
end if;
end loop;
end process;
end;
1.1 CVSROOT/VHDL/testing/TB_RC5KeyBreaker.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/TB_RC5KeyBreaker.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: TB_RC5KeyBreaker.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis
-- Create Date: 26/11/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TB_RC5KeyBreaker IS
END TB_RC5KeyBreaker;
ARCHITECTURE behavior OF TB_RC5KeyBreaker IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RC5KeyBreaker
PORT(
clk : IN std_logic;
go_in : IN std_logic;
key_range_in : IN std_logic_vector(39 downto 0);
yeah_out : OUT std_logic;
key_counter_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
constant half_clk_prd : time := 2.5 ns;
constant delta : time := 1 ns;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL go_in : std_logic := '0';
SIGNAL key_range_in : std_logic_vector(39 downto 0) := (others=>'0');
--Outputs
SIGNAL yeah_out : std_logic;
SIGNAL key_counter_out : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RC5KeyBreaker PORT MAP(
clk => clk,
go_in => go_in,
key_range_in => key_range_in,
yeah_out => yeah_out,
key_counter_out => key_counter_out
);
clk <= not(clk) after half_clk_prd;
-- good key = x"85fee1d4c0 53030cc9"
key_range_in <= x"85fee1d4c0" after 5*half_clk_prd + delta;
go_in <= '1' after 5*half_clk_prd + delta;
END;
1.1 CVSROOT/VHDL/testing/TB_long_shiftreg.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/TB_long_shiftreg.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: TB_long_shiftreg.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis
-- Create Date: 19/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_arith.all;
entity TB_long_shiftreg is
end TB_long_shiftreg;
architecture behavior of TB_long_shiftreg is
-- Component Declaration
component long_shiftreg
generic(
depthA : integer := 77; -- depth of shift register A (between 4 and 259)
depthB : integer := 69); -- depth of shift register B (between 4 and 259)
port(
clk : in std_logic;
A_in : in std_logic_vector (31 downto 0);
B_in : in std_logic_vector (31 downto 0);
A_out : out std_logic_vector (31 downto 0);
B_out : out std_logic_vector (31 downto 0));
end component;
constant n : integer := 32;
constant delayA : integer := 77;
constant delayB : integer := 69;
--Inputs
signal clk : std_logic := '0';
signal A_in,B_in : std_logic_vector(n-1 downto 0) := (others=>'0');
--Outputs
signal A_out,B_out : std_logic_vector(n-1 downto 0);
--User Defined
signal ok : std_logic;
constant half_clk_prd : time := 2.5 ns;
signal ResA,ResA_delayed,ResB,ResB_delayed : std_logic_vector(n-1 downto 0);
type delay_array_typeA is array (delayA-1 downto 0) of std_logic_vector(n-1 downto 0);
signal delay_arrayResA : delay_array_typeA;
type delay_array_typeB is array (delayB-1 downto 0) of std_logic_vector(n-1 downto 0);
signal delay_arrayResB : delay_array_typeB;
begin
-- Instantiate the Unit Under Test (UUT)
uut: long_shiftreg port map(clk,A_in,B_in,A_out,B_out);
clk <= not(clk) after half_clk_prd;
check_proc : process(clk)
begin
if rising_edge(clk) then
if (ResA_delayed = A_out) and (ResB_delayed = B_out) then
ok <= '1';
else
ok <= '0';
end if;
end if;
end process;
delay_shift_proc : process(clk)
begin
if rising_edge(clk) then
delay_arrayResA <= ResA & delay_arrayResA(delayA-1 downto 1);
delay_arrayResB <= ResB & delay_arrayResB(delayB-1 downto 1);
end if;
end process;
ResA_delayed <= delay_arrayResA(0);
ResB_delayed <= delay_arrayResB(0);
Data_input : process
file A_file,B_file : text;
variable INline: line;
variable INdata_n : bit_vector(n-1 downto 0);
variable A_tmp,B_tmp : std_logic_vector(n-1 downto 0);
begin
file_open(A_file,"TB_OperandA.tb",read_mode);
file_open(B_file,"TB_OperandB.tb",read_mode);
while true loop
wait until rising_edge(clk);
if not(endfile(A_file)) then
readline(A_file,INline);
read(INline,INdata_n);
A_tmp := To_StdLogicVector(INdata_n);
readline(B_file,INline);
read(INline,INdata_n);
B_tmp := To_StdLogicVector(INdata_n);
wait for 1 ns;
A_in <= A_tmp;
B_in <= B_tmp;
ResA <= A_tmp;
ResB <= B_tmp;
end if;
end loop;
end process;
end;
1.1 CVSROOT/VHDL/testing/TB_rotate_shiftreg.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/TB_rotate_shiftreg.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: TB_rotate_shiftreg.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis
-- Create Date: 19/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_arith.all;
entity TB_rotate_shiftreg is
end TB_rotate_shiftreg;
architecture behavior of TB_rotate_shiftreg is
-- Component Declaration
component rotate_shiftreg
generic(
rot_style : string := "intermediate"; -- "intermediate" or "deep"
include_last_stage : bit := '1'); -- include last stage of rotate ?
port(
clk : in std_logic;
X : in std_logic_vector (31 downto 0);
Y : in std_logic_vector (4 downto 0);
Z : out std_logic_vector (31 downto 0));
end component;
constant n : integer := 32;
constant rot_size : integer := 5;
constant delay : integer := 4; -- depend on rot_style and include_last_stage: 2,3 or 4,5
--Inputs
signal clk : std_logic := '0';
signal X_in : std_logic_vector(n-1 downto 0) := (others=>'0');
signal Y_in : std_logic_vector(rot_size-1 downto 0) := (others=>'0');
--Outputs
signal Z_out : std_logic_vector(n-1 downto 0);
--User Defined
signal ok : std_logic;
constant half_clk_prd : time := 2.5 ns;
signal Res,Res_delayed : std_logic_vector(n-1 downto 0);
type delay_array_type is array (delay-1 downto 0) of std_logic_vector(n-1 downto 0);
signal delay_arrayRes : delay_array_type;
begin
-- Instantiate the Unit Under Test (UUT)
uut: rotate_shiftreg port map(clk,X_in,Y_in,Z_out);
clk <= not(clk) after half_clk_prd;
check_proc : process(clk)
begin
if rising_edge(clk) then
if (Res_delayed = Z_out) then
ok <= '1';
else
ok <= '0';
end if;
end if;
end process;
delay_shift_proc : process(clk)
begin
if rising_edge(clk) then
delay_arrayRes <= Res & delay_arrayRes(delay-1 downto 1);
end if;
end process;
Res_delayed <= delay_arrayRes(0);
Data_input : process
file X_file,Res_file,Y_file : text;
variable INline: line;
variable INdata_n : bit_vector(n-1 downto 0);
variable INdata_rot_size : bit_vector(rot_size-1 downto 0);
variable X_tmp,Res_tmp : std_logic_vector(n-1 downto 0);
variable Y_tmp : std_logic_vector(rot_size-1 downto 0);
begin
file_open(X_file,"TB_OperandX.tb",read_mode);
file_open(Res_file,"TB_Res.tb",read_mode);
file_open(Y_file,"TB_OperandY.tb",read_mode);
while true loop
wait until rising_edge(clk);
if not(endfile(X_file)) then
readline(X_file,INline);
read(INline,INdata_n);
X_tmp := To_StdLogicVector(INdata_n);
readline(Res_file,INline);
read(INline,INdata_n);
Res_tmp := To_StdLogicVector(INdata_n);
readline(Y_file,INline);
read(INline,INdata_rot_size);
Y_tmp := To_StdLogicVector(INdata_rot_size);
wait for 1 ns;
X_in <= X_tmp;
Res <= Res_tmp;
Y_in <= Y_tmp;
end if;
end loop;
end process;
end;
1.1 CVSROOT/VHDL/testing/cstPack.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/testing/cstPack.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: cstPack.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis
-- Create Date: 31/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package cstPack is
--constant Ciphertext_contest : bit_vector := x"a6ec745fbefcafe7"; -- Contest identifier: RC5-32/12/9
constant Ciphertext_contest : bit_vector := x"2fb7852a562d285a"; -- Test Pseudo-Contests identifier: RC5-32/12/9
--constant Plaintext_contest : bit_vector := x"989E14756CF2BD15"; -- "The unkn" (= x"6e6b6e7520656854") xor IV (= x"f6f57a004c97d541")
constant Plaintext_contest : bit_vector := x"2FF17AF33F3CA653"; -- "The unkn" (= x"6e6b6e7520656854") xor IV (= x"419a14861f59ce07")
-- corresponding key for the Test Pseudo-Contests: x"85fee1d4c053030cc9"
constant S32_cst : bit_vector := x"b7e15163";
constant T32_cst : bit_vector := x"9e3779b9";
constant n: integer := 32;
constant r_cst : integer := 12; -- number of rounds
constant t_cst : integer := 2*(r_cst+1); -- number of keySchedule elements
constant rot_style_keysched: string := "small";-- "small", "intermediate" or "deep"
constant rot_style_encr: string := "intermediate";-- "small", "intermediate" or "deep"
constant include_last_stage_keysched: bit := '0';-- include last stage of rotate ?
constant include_last_stage_encr: bit := '0';-- include last stage of rotate ?
constant delayRot_keysched : integer := 2; -- because of rot_style and include_last_stage
constant delayRot_encr : integer := 3; -- because of rot_style and include_last_stage
constant delay_Asig: integer := delayRot_keysched +2 -1;
-- those constants have a strong impact on the last set of Shift Registers on the S signal.
constant delayKeyScheduleBox : integer := delayRot_keysched + 4 -1; -- "-1" because A and S are processed 1 cycle before B
constant delaySregister : integer := delayKeyScheduleBox*(t_cst-1) + (delayRot_keysched+1);
constant offset_delayLastS : integer := t_cst-1; -- without delay_Asig(=delay_Ssig)
constant delay_Brot_cmd : integer := delayRot_keysched;
constant delay_Lout_cmd : integer := 3*delayKeyScheduleBox-1;
constant delay_Lout : integer := delay_Lout_cmd - delayRot_keysched;
constant total_delay : integer := 3*t_cst*delayKeyScheduleBox -(delayRot_keysched+1) +1;
constant in_Ptxt_delay : integer := 2*t_cst*delayKeyScheduleBox +2 +(delayRot_keysched+3); -- useful for simulation
end cstPack;
package body cstPack is
end cstPack;
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