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From: cvs at opencores.org<cvs@o...>
Date: Tue Nov 28 01:41:41 CET 2006
Subject: [cvs-checkins] MODIFIED: CVSROOT ...
Date: 00/06/11 28:01:41

Added: CVSROOT/VHDL/shared_files CompoPack.vhd EncryptBloc.vhd
EncryptBloc_last.vhd KeyScheduleBloc.vhd
RC5KeyBreaker.ucf RC5KeyBreaker.vhd RC5encrypt.vhd
XOR32.vhd add32.vhd add32mux0_16.vhd cstPack.vhd
delay_shiftreg.vhd delay_shiftreg_bit.vhd
mux0_16.vhd rotate3.vhd rotate_shiftreg.vhd
Log:
Here it is (at last).

In the folder "shared_files" are the files used for most of the configurations

Specific files for specific platforms lies in other folders.

The folder "testing" embed the test benches as well as a python script used to generate test data files (and to help generating code for TB.vhd files).



Using_LbRAMs replace regular shift register by shift registers based on bRAMs.



Currently, the real difference between platforms is the way "long_shiftReg" is implemented (because bRAMS instanciation is different).



Enjoy!

--

Guerric


Revision Changes Path
1.1 CVSROOT/VHDL/shared_files/CompoPack.vhd

http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/CompoPack.vhd?rev=1.1&content-type=text/x-cvsweb-markup

Index: CompoPack.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis
-- Create Date: 23/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

use WORK.cstPack.all;

package CompoPack is

component rotate_shiftreg
generic(
rot_style : string;
include_last_stage : bit);
port(
clk : in std_logic;
X : in std_logic_vector (n-1 downto 0);
Y : in std_logic_vector (4 downto 0);
Z : out std_logic_vector (n-1 downto 0));
end component;

component delay_shiftreg
generic(
n : integer;
delay : integer);
port(
clk : in std_logic;
sig_in : in std_logic_vector (n-1 downto 0);
sig_out : out std_logic_vector (n-1 downto 0));
end component;

component delay_shiftreg_bit
generic(
delay : integer);
port(
clk : in std_logic;
sig_in : in std_logic;
sig_out : out std_logic);
end component;

component mux0_16
port(
clk : in std_logic;
A_in : in std_logic_vector (n-1 downto 0);
cmd : in std_logic;
C_out : out std_logic_vector (n-1 downto 0));
end component;

component add32
port( clk : in std_logic; A_in,B_in : in std_logic_vector (n-1 downto 0); C_out : out std_logic_vector (n-1 downto 0)); end component; component add32mux0_16 port( clk : in std_logic; A_in,B_in : in std_logic_vector (n-1 downto 0); cmd : in std_logic; C_out : out std_logic_vector (n-1 downto 0)); end component; component rotate3 port( X_in : in std_logic_vector (n-1 downto 0); X_out : out std_logic_vector (n-1 downto 0)); end component; component xor32 port( clk : in std_logic; A_in,B_in : in std_logic_vector (n-1 downto 0); C_out : out std_logic_vector (n-1 downto 0)); end component; component long_shiftreg generic( depthA : integer; -- depth of shift register A (between 4 and 259) depthB : integer); -- depth of shift register B (between 4 and 259) port( clk : in std_logic; A_in : in std_logic_vector (n-1 downto 0); B_in : in std_logic_vector (n-1 downto 0); A_out : out std_logic_vector (n-1 downto 0); B_out : out std_logic_vector (n-1 downto 0)); end component; component KeyScheduleBloc generic( delay_Asig : integer := delay_Asig; delay_Brot_cmd : integer := delay_Brot_cmd; delay_Lout_cmd : integer := delay_Lout_cmd; delay_Lout : integer := delay_Lout); port( clk : in std_logic; A_in,S_in,B_in,L_in : in std_logic_vector (31 downto 0); B_in_rot_cmd,L_in_rot_cmd : in std_logic; A_out,S_out,B_out,L_out : out std_logic_vector (31 downto 0); B_out_rot_cmd,L_out_rot_cmd : out std_logic); end component; component EncryptBloc port( clk : in std_logic; P_in,Q_in,S1,S2 : in std_logic_vector (31 downto 0); P_out,Q_out : out std_logic_vector (31 downto 0)); end component; component EncryptBloc_last port( clk : in std_logic; P_in,Q_in,S1,S2 : in std_logic_vector (n-1 downto 0); ok_P,ok_Q : out std_logic); end component; component RC5encrypt port( clk : in std_logic; key : in std_logic_vector (3*n-1 downto 0); Plaintext : in std_logic_vector(2*n-1 downto 0); ok_P,ok_Q : out std_logic); end component; end CompoPack; package body CompoPack is end CompoPack; 1.1 CVSROOT/VHDL/shared_files/EncryptBloc.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/EncryptBloc.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: EncryptBloc.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 30/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use WORK.CompoPack.all; use WORK.cstPack.all; entity EncryptBloc is port( clk : in std_logic; P_in,Q_in,S1,S2 : in std_logic_vector (31 downto 0); P_out,Q_out : out std_logic_vector (31 downto 0)); end EncryptBloc; architecture EncryptBloc_arch of EncryptBloc is --constant n : integer := 32; signal xorPQ1,xorPQ2,rot_out1,rot_out2,Ptmp,Qtmp : std_logic_vector(n-1 downto 0); signal rotn_cmd1,rotn_cmd2 : std_logic_vector(4 downto 0); signal rot_out1_rot_cmd,rot_out2_rot_cmd : std_logic; begin xor32_1: xor32 port map(clk,P_in,Q_in,xorPQ1); shiftreg1: delay_shiftreg generic map(5,1) port map(clk,Q_in(4 downto 0),rotn_cmd1); rotn1: rotate_shiftreg generic map(rot_style_encr,include_last_stage_encr) port map(clk,xorPQ1,rotn_cmd1,rot_out1); shiftreg2: delay_shiftreg_bit generic map(delayRot_encr) port map(clk,rotn_cmd1(4),rot_out1_rot_cmd); add1: add32mux0_16 port map(clk,S1,rot_out1,rot_out1_rot_cmd,Ptmp); shiftreg3: delay_shiftreg generic map(n,2+delayRot_encr) port map(clk,Ptmp,P_out); shiftreg4: delay_shiftreg generic map(n,2+delayRot_encr) port map(clk,Q_in,Qtmp); xor32_2: xor32 port map(clk,Ptmp,Qtmp,xorPQ2); shiftreg5: delay_shiftreg generic map(5,1) port map(clk,Ptmp(4 downto 0),rotn_cmd2); rotn2: rotate_shiftreg generic map(rot_style_encr,include_last_stage_encr) port map(clk,xorPQ2,rotn_cmd2,rot_out2); shiftreg6: delay_shiftreg_bit generic map(delayRot_encr) port map(clk,rotn_cmd2(4),rot_out2_rot_cmd); add2: add32mux0_16 port map(clk,S2,rot_out2,rot_out2_rot_cmd,Q_out); end EncryptBloc_arch; 1.1 CVSROOT/VHDL/shared_files/EncryptBloc_last.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/EncryptBloc_last.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: EncryptBloc_last.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 30/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use WORK.CompoPack.all; use WORK.cstPack.all; entity EncryptBloc_last is port( clk : in std_logic; P_in,Q_in,S1,S2 : in std_logic_vector (31 downto 0); ok_P,ok_Q : out std_logic); end EncryptBloc_last; architecture EncryptBloc_last_arch of EncryptBloc_last is --constant n : integer := 32; signal xorPQ1,xorPQ2,rot_out1,rot_out2,Ptmp,Qtmp : std_logic_vector(n-1 downto 0); signal rotn_cmd1,rotn_cmd2 : std_logic_vector(4 downto 0); signal rot_out1_rot_cmd,rot_out2_rot_cmd : std_logic; signal Ctxt : std_logic_vector(2*n-1 downto 0) := To_StdLogicVector(Ciphertext_contest); signal ok_Ptmp : std_logic; signal Q_out : std_logic_vector(n-1 downto 0); begin xor32_1: xor32 port map(clk,P_in,Q_in,xorPQ1); shiftreg1: delay_shiftreg generic map(5,1) port map(clk,Q_in(4 downto 0),rotn_cmd1); rotn1: rotate_shiftreg generic map(rot_style_encr,include_last_stage_encr) port map(clk,xorPQ1,rotn_cmd1,rot_out1); shiftreg2: delay_shiftreg_bit generic map(delayRot_encr) port map(clk,rotn_cmd1(4),rot_out1_rot_cmd); add1: add32mux0_16 port map(clk,S1,rot_out1,rot_out1_rot_cmd,Ptmp); --shiftreg3: delay_shiftreg generic map(n,2+delayRot_encr) port map(clk,Ptmp,P_out); shiftreg4: delay_shiftreg generic map(n,2+delayRot_encr) port map(clk,Q_in,Qtmp); xor32_2: xor32 port map(clk,Ptmp,Qtmp,xorPQ2); shiftreg5: delay_shiftreg generic map(5,1) port map(clk,Ptmp(4 downto 0),rotn_cmd2); rotn2: rotate_shiftreg generic map(rot_style_encr,include_last_stage_encr) port map(clk,xorPQ2,rotn_cmd2,rot_out2); shiftreg6: delay_shiftreg_bit generic map(delayRot_encr) port map(clk,rotn_cmd2(4),rot_out2_rot_cmd); add2: add32mux0_16 port map(clk,S2,rot_out2,rot_out2_rot_cmd,Q_out); check_proc: process(clk) begin if rising_edge(clk) then if Ptmp = Ctxt(n-1 downto 0) then ok_Ptmp <= '1'; else ok_Ptmp <= '0'; end if; if Q_out = Ctxt(2*n-1 downto n) then ok_Q <= '1'; else ok_Q <= '0'; end if; end if; end process; shiftreg7: delay_shiftreg_bit generic map(2+delayRot_encr) port map(clk,ok_Ptmp,ok_P); end EncryptBloc_last_arch; 1.1 CVSROOT/VHDL/shared_files/KeyScheduleBloc.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/KeyScheduleBloc.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: KeyScheduleBloc.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 23/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use WORK.CompoPack.all; use WORK.cstPack.all; entity KeyScheduleBloc is generic( delay_Asig : integer := 3; delay_Brot_cmd : integer := 2; delay_Lout_cmd : integer := 14; delay_Lout : integer := 12); -- delay_Lout_cmd - rotate depth port( clk : in std_logic; A_in,S_in,B_in,L_in : in std_logic_vector (31 downto 0); B_in_rot_cmd,L_in_rot_cmd : in std_logic; A_out,S_out,B_out,L_out : out std_logic_vector (31 downto 0); B_out_rot_cmd,L_out_rot_cmd : out std_logic); end KeyScheduleBloc; architecture KeyScheduleBloc_arch of KeyScheduleBloc is signal add_AS,add_ASB,add_ASBrot3,mux_B,add_AoutBmux,add_L,rot_out: std_logic_vector(n-1 downto 0); signal rotn_cmd : std_logic_vector(4 downto 0); begin add1: add32 port map(clk,A_in,S_in,add_AS); add2: add32mux0_16 port map(clk,add_AS,B_in,B_in_rot_cmd,add_ASB); rot31: rotate3 port map(add_ASB,add_ASBrot3); S_out <= add_ASBrot3; shiftreg1: delay_shiftreg generic map(n,delay_Asig) port map(clk,add_ASBrot3,A_out); mux1: mux0_16 port map(clk,B_in,B_in_rot_cmd,mux_B); add3: add32 port map(clk,add_ASBrot3,mux_B,add_AoutBmux); shiftreg2: delay_shiftreg generic map(5,1) port map(clk,add_AoutBmux(4 downto 0),rotn_cmd); add4: add32mux0_16 port map(clk,add_AoutBmux,L_in,L_in_rot_cmd,add_L); rotn1: rotate_shiftreg generic map(rot_style_keysched,include_last_stage_keysched) port map(clk,add_L,rotn_cmd,rot_out); B_out <= rot_out; shiftreg3: delay_shiftreg_bit generic map(delay_Brot_cmd) port map(clk,rotn_cmd(4),B_out_rot_cmd); shiftreg4: delay_shiftreg_bit generic map(delay_Lout_cmd) port map(clk,rotn_cmd(4),L_out_rot_cmd); shiftreg5: delay_shiftreg generic map(n,delay_Lout) port map(clk,rot_out,L_out); end KeyScheduleBloc_arch; 1.1 CVSROOT/VHDL/shared_files/RC5KeyBreaker.ucf http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/RC5KeyBreaker.ucf?rev=1.1&content-type=text/x-cvsweb-markup Index: RC5KeyBreaker.ucf =================================================================== NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 4.35 ns HIGH 50 %; 1.1 CVSROOT/VHDL/shared_files/RC5KeyBreaker.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/RC5KeyBreaker.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: RC5KeyBreaker.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 7/11/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use WORK.cstPack.all; use WORK.compoPack.all; entity RC5KeyBreaker is port( -- it is assumed that the user can store the previous key_range. As a result, only the counter is provided when the key matches clk, go_in : in std_logic; key_range_in : in std_logic_vector (39 downto 0); yeah_out : out std_logic; key_counter_out : out std_logic_vector (n-1 downto 0)); end RC5KeyBreaker; architecture RC5KeyBreaker_arch of RC5KeyBreaker is signal Ptxt : std_logic_vector(2*n-1 downto 0) := To_StdLogicVector(Plaintext_contest); signal ok_P,ok_Q : std_logic; signal go,go_reg,yeah,yeah_reg : std_logic; signal key_counter,key_counter_reg : std_logic_vector(n-1 downto 0); signal counter_main : std_logic_vector(n downto 0) := "100000000000000000000000000000001"; signal counter_mirror : std_logic_vector(n-1 downto 0) := x"00000000"; signal delay_counter : std_logic_vector(9 downto 0) := "0000000000"; -- depends on the size of "total_delay" signal key : std_logic_vector(3*n-1 downto 0); signal key_range_effective,key_range,key_range_reg : std_logic_vector (39 downto 0); type state_type is (S1,S2); signal state : state_type := S1; begin RC5_compo: RC5encrypt port map(clk,key,Ptxt,ok_P,ok_Q); finding_proc: process(clk) begin if rising_edge(clk) then if (ok_P = '1') and (ok_Q = '1') then yeah <= '1'; else yeah <= '0'; end if; end if; end process; reg_proc: process(clk) begin if rising_edge(clk) then go_reg <= go_in; go <= go_reg; key_range_reg <= key_range_in; key_range <= key_range_reg; yeah_reg <= yeah; yeah_out <= yeah_reg; key_counter_reg <= key_counter; key_counter_out <= key_counter_reg; if yeah = '1' then key_counter <= counter_mirror; end if; end if; end process; -- Probably not yet compatible with distributed.net concerning the way to increment the counter -- there is 2 counters. The main and a mirror with an offset of the total delay of the pipeline count_proc: process(clk) begin if rising_edge(clk) then if counter_main(32) = '1' then delay_counter <= CONV_STD_LOGIC_VECTOR(total_delay -4 + 2 +1, 10); -- +2 comes from the addition of 2 registers for testing the output. +1 because there is a difference of 1 between the init of the two counters if go = '1' then key_range_effective <= key_range; counter_main <= CONV_STD_LOGIC_VECTOR(1, 33); -- else -- wait for the new key_range -- no counter increment end if; else counter_main <= counter_main + 1; if delay_counter(9) = '0' then -- not mandatory delay_counter <= delay_counter -1; end if; end if; end if; end process; mirror_count_process : process(clk) begin if rising_edge(clk) then case state is when S1 => -- Wait and Load phase 1 if (delay_counter(9) = '1') then state <= S2; counter_mirror <= CONV_STD_LOGIC_VECTOR(0, 32); else state <= S1; counter_mirror <= counter_mirror + 1; end if; when S2 => -- Load phase 2 counter_mirror <= counter_mirror + 1; if (counter_main(32) = '1') then state <= S1; else state <= S2; end if; end case; end if; end process; key <= x"000000" & key_range_effective & counter_main(n-1 downto 0); end RC5KeyBreaker_arch; 1.1 CVSROOT/VHDL/shared_files/RC5encrypt.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/RC5encrypt.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: RC5encrypt.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 31/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use WORK.CompoPack.all; use WORK.cstPack.all; entity RC5encrypt is port( clk : in std_logic; key : in std_logic_vector (3*n-1 downto 0); Plaintext : in std_logic_vector(2*n-1 downto 0); ok_P,ok_Q : out std_logic); end RC5encrypt; architecture RC5encrypt_arch of RC5encrypt is type ABStmp_array_type is array (3*t_cst downto 0) of std_logic_vector(n-1 downto 0); signal A,B,Stmp : ABStmp_array_type; signal B_rot_cmd : std_logic_vector(3*t_cst downto 0); type S_array_type is array (4*t_cst downto 0) of std_logic_vector(n-1 downto 0); signal S : S_array_type; type L_array_type is array (3*t_cst-1+3 downto 0) of std_logic_vector(n-1 downto 0); signal L : L_array_type; signal L_rot_cmd : std_logic_vector(3*t_cst-1+3 downto 0); type PQ_array_type is array (r_cst downto 0) of std_logic_vector(n-1 downto 0); signal P,Q : PQ_array_type; begin -- KeySchedule Blocs init S(0) <= To_StdLogicVector(S32_cst); gen_Sinit: for i in 1 to t_cst-1 generate begin S(i) <= S(i-1) + To_StdLogicVector(T32_cst); end generate; ShRegL0 : delay_shiftreg generic map(n,3) port map(clk,key(n-1 downto 0),L(0)); ShRegL1 : delay_shiftreg generic map(n,delayKeyScheduleBox+3) port map(clk,key(2*n-1 downto n),L(1)); ShRegL2 : delay_shiftreg generic map(n,2*delayKeyScheduleBox+3) port map(clk,key(3*n-1 downto 2*n),L(2)); L_rot_cmd(2 downto 0) <= "000"; A(0) <= (others=>'0'); B(0) <= (others=>'0'); B_rot_cmd(0) <= '0'; -- KeySchedule Blocs gen_KeySchedMap: for i in 0 to 3*t_cst-1 generate begin KeySchedMap: KeyScheduleBloc port map(clk,A(i),S(i),B(i),L(i),B_rot_cmd(i),L_rot_cmd(i),A(i+1),Stmp(i),B(i+1),L(i+3),B_rot_cmd(i+1),L_rot_cmd(i+3)); end generate; gen_KeySchedShReg: for i in 0 to t_cst-1 generate begin KeySchedShRegMap: long_shiftreg generic map(delaySregister,delaySregister) port map(clk,Stmp(2*i),Stmp(2*i+1),S(t_cst+2*i),S(t_cst+2*i+1)); end generate; ---- gen_KeySchedShReg3: for i in 1 to r_cst generate -- !!! ---- begin -- clearly depends on the difference between the number of pipeline stages in both KeyBloc and EncryptBloc ---- KeySchedShReg3Map: long_shiftreg generic map(offset_delayLastS -(2*i),offset_delayLastS -(2*i+1)) port map(clk,Stmp(2*t_cst+2*i),Stmp(2*t_cst+2*i+1),S(3*t_cst+2*i),S(3*t_cst+2*i+1)); ---- end generate; ---- firstShReg3Map: long_shiftreg generic map(offset_delayLastS+delayRot_keysched+2,offset_delayLastS -1) port map(clk,Stmp(2*t_cst),Stmp(2*t_cst+1),S(3*t_cst),S(3*t_cst+1)); gen_KeySchedShReg3: for i in 1 to t_cst-1 generate begin -- clearly depends on the difference between the number of pipeline stages in both KeyBloc and EncryptBloc S(3*t_cst+i) <= Stmp(2*t_cst+i); end generate; firstShReg3Map: delay_shiftreg generic map(n,delayRot_keysched+3) port map(clk,Stmp(2*t_cst),S(3*t_cst)); -- Encrypt Blocs init add_initEncrypt1: add32 port map(clk,Plaintext(n-1 downto 0),S(3*t_cst),P(0)); add_initEncrypt2: add32 port map(clk,Plaintext(2*n-1 downto n),S(3*t_cst+1),Q(0)); -- Encrypt Blocs gen_EncryptMap: for i in 0 to r_cst-2 generate begin encryptMap: EncryptBloc port map(clk,P(i),Q(i),S(3*t_cst+2+2*i),S(3*t_cst+2+2*i+1),P(i+1),Q(i+1)); end generate; encryptMap_last: EncryptBloc_last port map(clk,P(r_cst-1),Q(r_cst-1),S(3*t_cst+2+2*(r_cst-1)),S(3*t_cst+2+2*(r_cst-1)+1),ok_P,ok_Q); end RC5encrypt_arch; 1.1 CVSROOT/VHDL/shared_files/XOR32.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/XOR32.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: XOR32.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 23/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --library UNISIM; --use UNISIM.VComponents.all; entity xor32 is port( clk : in std_logic; A_in,B_in : in std_logic_vector (31 downto 0); C_out : out std_logic_vector (31 downto 0)); end xor32; architecture xor32_arch of xor32 is begin proc_reg: process(clk) begin if rising_edge(clk) then C_out <= A_in xor B_in; end if; end process; end xor32_arch; 1.1 CVSROOT/VHDL/shared_files/add32.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/add32.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: add32.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 23/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --library UNISIM; --use UNISIM.VComponents.all; entity add32 is port( clk : in std_logic; A_in,B_in : in std_logic_vector (31 downto 0); C_out : out std_logic_vector (31 downto 0)); end add32; architecture add32_arch_virtex of add32 is constant n: integer := 32; signal C_br: std_logic_vector(n-1 downto 0); begin C_br <= A_in + B_in; proc_reg: process(clk) begin if rising_edge(clk) then C_out <= C_br; end if; end process; end add32_arch_virtex; 1.1 CVSROOT/VHDL/shared_files/add32mux0_16.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/add32mux0_16.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: add32mux0_16.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 23/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --library UNISIM; --use UNISIM.VComponents.all; entity add32mux0_16 is port( clk : in std_logic; A_in,B_in : in std_logic_vector (31 downto 0); cmd : in std_logic; C_out : out std_logic_vector (31 downto 0)); end add32mux0_16; architecture add32mux0_16_arch_virtex of add32mux0_16 is constant n: integer := 32; signal B,C_br: std_logic_vector(n-1 downto 0); begin with cmd select B <= B_in when '0', B_in(n-17 downto 0) & B_in(n-1 downto n-16) when others; -- rotate 16 C_br <= A_in + B; proc_reg: process(clk) begin if rising_edge(clk) then C_out <= C_br; end if; end process; end add32mux0_16_arch_virtex; 1.1 CVSROOT/VHDL/shared_files/cstPack.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/cstPack.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: cstPack.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 31/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; package cstPack is constant Ciphertext_contest : bit_vector := x"a6ec745fbefcafe7"; -- Contest identifier: RC5-32/12/9 constant Plaintext_contest : bit_vector := x"989E14756CF2BD15"; -- "The unkn" (= x"6e6b6e7520656854") xor IV (= x"f6f57a004c97d541") constant S32_cst : bit_vector := x"b7e15163"; constant T32_cst : bit_vector := x"9e3779b9"; constant n: integer := 32; constant r_cst : integer := 12; -- number of rounds constant t_cst : integer := 2*(r_cst+1); -- number of keySchedule elements constant rot_style_keysched: string := "small";-- "small", "intermediate" or "deep" constant rot_style_encr: string := "intermediate";-- "small", "intermediate" or "deep" constant include_last_stage_keysched: bit := '0';-- include last stage of rotate ? constant include_last_stage_encr: bit := '0';-- include last stage of rotate ? constant delayRot_keysched : integer := 2; -- because of rot_style and include_last_stage constant delayRot_encr : integer := 3; -- because of rot_style and include_last_stage constant delay_Asig: integer := delayRot_keysched +2 -1; -- those constants have a strong impact on the last set of Shift Registers on the S signal. constant delayKeyScheduleBox : integer := delayRot_keysched + 4 -1; -- "-1" because A and S are processed 1 cycle before B constant delaySregister : integer := delayKeyScheduleBox*(t_cst-1) + (delayRot_keysched+1); constant offset_delayLastS : integer := t_cst-1; -- without delay_Asig(=delay_Ssig) constant delay_Brot_cmd : integer := delayRot_keysched; constant delay_Lout_cmd : integer := 3*delayKeyScheduleBox-1; constant delay_Lout : integer := delay_Lout_cmd - delayRot_keysched; constant total_delay : integer := 3*t_cst*delayKeyScheduleBox -(delayRot_keysched+1) +1; constant in_Ptxt_delay : integer := 2*t_cst*delayKeyScheduleBox +2 +(delayRot_keysched+3); -- useful for simulation end cstPack; package body cstPack is end cstPack; 1.1 CVSROOT/VHDL/shared_files/delay_shiftreg.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/delay_shiftreg.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: delay_shiftreg.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Ack: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 19/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; --library UNISIM; --use UNISIM.VComponents.all; entity delay_shiftreg is generic( n : integer := 1; delay : integer := 1); port( clk : in std_logic; sig_in : in std_logic_vector (n-1 downto 0); sig_out : out std_logic_vector (n-1 downto 0)); end delay_shiftreg; architecture behav of delay_shiftreg is begin delay0_gen: if (delay=0) generate begin sig_out <= sig_in; end generate; delay1_gen: if (delay=1) generate begin delay1_shift_proc : process(clk) begin if rising_edge(clk) then sig_out <= sig_in; end if; end process; end generate; delay_gen_bign: if ((delay>1) and n>1) generate type n_delay_array_type is array (delay-1 downto 0) of std_logic_vector(n-1 downto 0); signal n_delay_array : n_delay_array_type; begin delay_shift_proc : process(clk) begin if rising_edge(clk) then n_delay_array <= sig_in & n_delay_array(delay-1 downto 1); end if; end process; sig_out <= n_delay_array(0); end generate; delay_gen_n1: if ((delay>1) and n=1) generate signal n_delay_vect : std_logic_vector(delay-1 downto 0); begin delay_shift_proc : process(clk) begin if rising_edge(clk) then n_delay_vect <= sig_in & n_delay_vect(delay-1 downto 1); end if; end process; sig_out(0) <= n_delay_vect(0); end generate; end behav; 1.1 CVSROOT/VHDL/shared_files/delay_shiftreg_bit.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/delay_shiftreg_bit.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: delay_shiftreg_bit.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Ack: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 19/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; --library UNISIM; --use UNISIM.VComponents.all; entity delay_shiftreg_bit is generic( delay : integer := 1); port( clk : in std_logic; sig_in : in std_logic; sig_out : out std_logic); end delay_shiftreg_bit; architecture behav of delay_shiftreg_bit is begin delay0_gen: if (delay=0) generate begin sig_out <= sig_in; end generate; delay1_gen: if (delay=1) generate begin delay1_shift_proc : process(clk) begin if rising_edge(clk) then sig_out <= sig_in; end if; end process; end generate; delay_gen: if (delay>1) generate signal n_delay_vect : std_logic_vector(delay-1 downto 0); begin delay_shift_proc : process(clk) begin if rising_edge(clk) then n_delay_vect <= sig_in & n_delay_vect(delay-1 downto 1); end if; end process; sig_out <= n_delay_vect(0); end generate; end behav; 1.1 CVSROOT/VHDL/shared_files/mux0_16.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/mux0_16.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: mux0_16.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 23/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --library UNISIM; --use UNISIM.VComponents.all; entity mux0_16 is port( clk : in std_logic; A_in : in std_logic_vector (31 downto 0); cmd : in std_logic; C_out : out std_logic_vector (31 downto 0)); end mux0_16; architecture behav of mux0_16 is constant n: integer := 32; signal C_br: std_logic_vector(n-1 downto 0); begin with cmd select C_br <= A_in when '0', A_in(n-17 downto 0) & A_in(n-1 downto n-16) when others; -- rotate 16 proc_reg: process(clk) begin if rising_edge(clk) then C_out <= C_br; end if; end process; end behav; 1.1 CVSROOT/VHDL/shared_files/rotate3.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/rotate3.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: rotate3.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 23/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --library UNISIM; --use UNISIM.VComponents.all; -- Rotate left entity rotate3 is port( X_in : in std_logic_vector (31 downto 0); X_out : out std_logic_vector (31 downto 0)); end rotate3; architecture behav of rotate3 is constant n: integer := 32; begin X_out <= X_in(n-4 downto 0) & X_in(n-1 downto n-3); end behav; 1.1 CVSROOT/VHDL/shared_files/rotate_shiftreg.vhd http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/shared_files/rotate_shiftreg.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: rotate_shiftreg.vhd =================================================================== ---------------------------------------------------------------------------------- -- Univeriste catholique de Louvain -- UCL DICE/Crypto Group -- Place du Levant, 3 -- B-1348 Louvain-la-Neuve -- Belgium -- -- Guerric Meurice de Dormale -- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis -- Create Date: 19/10/2006 ---------------------------------------------------------------------------------- -- This may freely be used, as long as copyright notices are maintained per BSD licensing -- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --library UNISIM; --use UNISIM.VComponents.all; -- Rotate Left Shift Register entity rotate_shiftreg is generic( rot_style : string := "intermediate"; -- "small", "intermediate" or "deep" include_last_stage : bit := '0'); -- include last stage of rotate ? port( clk : in std_logic; X : in std_logic_vector (31 downto 0); Y : in std_logic_vector (4 downto 0); Z : out std_logic_vector (31 downto 0)); end rotate_shiftreg; architecture rotate_shiftreg_arch_Virtex of rotate_shiftreg is constant n : integer := 32; component delay_shiftreg generic ( n : integer; -- bit_size of input delay : integer); port( clk : in std_logic; sig_in : in std_logic_vector (n-1 downto 0); sig_out : out std_logic_vector (n-1 downto 0)); end component; begin gen_deep_laststage1: if (rot_style = "deep") and (include_last_stage='1') generate type rot_array_type is array (4 downto 0) of std_logic_vector(n-1 downto 0); signal rot_array,rot_array_br : rot_array_type; signal Y_delayed : std_logic_vector(4 downto 0); begin Y_delayed(0) <= Y(0); gen_delay_Y: for i in 1 to 4 generate comp_delay: delay_shiftreg generic map(1,i) port map(clk,Y(i downto i),Y_delayed(i downto i)); end generate; with Y_delayed(0) select rot_array_br(0) <= X when '0', X(n-2 downto 0) & X(n-1) when others; -- rotate 1 with Y_delayed(1) select rot_array_br(1) <= rot_array(0) when '0', rot_array(0)(n-3 downto 0) & rot_array(0)(n-1 downto n-2) when others; -- rotate 2 with Y_delayed(2) select rot_array_br(2) <= rot_array(1) when '0', rot_array(1)(n-5 downto 0) & rot_array(1)(n-1 downto n-4) when others; -- rotate 4 with Y_delayed(3) select rot_array_br(3) <= rot_array(2) when '0', rot_array(2)(n-9 downto 0) & rot_array(2)(n-1 downto n-8) when others; -- rotate 8 with Y_delayed(4) select rot_array_br(4) <= rot_array(3) when '0', rot_array(3)(n-17 downto 0) & rot_array(3)(n-1 downto n-16) when others; -- rotate 16 proc_reg: process(clk) begin if rising_edge(clk) then rot_array <= rot_array_br; end if; end process; Z <= rot_array(4); end generate; gen_deep_laststage0: if (rot_style = "deep") and (include_last_stage='0') generate type rot_array_type is array (3 downto 0) of std_logic_vector(n-1 downto 0); signal rot_array,rot_array_br : rot_array_type; signal Y_delayed : std_logic_vector(3 downto 0); begin Y_delayed(0) <= Y(0); gen_delay_Y: for i in 1 to 3 generate comp_delay: delay_shiftreg generic map(1,i) port map(clk,Y(i downto i),Y_delayed(i downto i)); end generate; with Y_delayed(0) select rot_array_br(0) <= X when '0', X(n-2 downto 0) & X(n-1) when others; -- rotate 1 with Y_delayed(1) select rot_array_br(1) <= rot_array(0) when '0', rot_array(0)(n-3 downto 0) & rot_array(0)(n-1 downto n-2) when others; -- rotate 2 with Y_delayed(2) select rot_array_br(2) <= rot_array(1) when '0', rot_array(1)(n-5 downto 0) & rot_array(1)(n-1 downto n-4) when others; -- rotate 4 with Y_delayed(3) select rot_array_br(3) <= rot_array(2) when '0', rot_array(2)(n-9 downto 0) & rot_array(2)(n-1 downto n-8) when others; -- rotate 8 proc_reg: process(clk) begin if rising_edge(clk) then rot_array <= rot_array_br; end if; end process; Z <= rot_array(3); end generate; gen_intermediate_laststage1: if (rot_style = "intermediate") and (include_last_stage='1') generate type rot_array_type is array (3 downto 0) of std_logic_vector(n-1 downto 0); signal rot_array,rot_array_br : rot_array_type; signal Y_delayed : std_logic_vector(4 downto 0); begin Y_delayed(0) <= Y(0); comp_delay1: delay_shiftreg generic map(2,1) port map(clk,Y(2 downto 1),Y_delayed(2 downto 1)); comp_delay2: delay_shiftreg generic map(1,2) port map(clk,Y(3 downto 3),Y_delayed(3 downto 3)); comp_delay3: delay_shiftreg generic map(1,3) port map(clk,Y(4 downto 4),Y_delayed(4 downto 4)); with Y_delayed(0) select rot_array_br(0) <= X when '0', X(n-2 downto 0) & X(n-1) when others; -- rotate 1 with Y_delayed(2 downto 1) select rot_array_br(1) <= rot_array(0) when "00", rot_array(0)(n-3 downto 0) & rot_array(0)(n-1 downto n-2) when "01", -- rotate 2 rot_array(0)(n-5 downto 0) & rot_array(0)(n-1 downto n-4) when "10", -- rotate 4 rot_array(0)(n-7 downto 0) & rot_array(0)(n-1 downto n-6) when others; -- rotate 6 with Y_delayed(3) select rot_array_br(2) <= rot_array(1) when '0', rot_array(1)(n-9 downto 0) & rot_array(1)(n-1 downto n-8) when others; -- rotate 8 with Y_delayed(4) select rot_array_br(3) <= rot_array(2) when '0', rot_array(2)(n-17 downto 0) & rot_array(2)(n-1 downto n-16) when others; -- rotate 16 proc_reg: process(clk) begin if rising_edge(clk) then rot_array <= rot_array_br; end if; end process; Z <= rot_array(3); end generate; gen_intermediate_laststage0: if (rot_style = "intermediate") and (include_last_stage='0') generate type rot_array_type is array (2 downto 0) of std_logic_vector(n-1 downto 0); signal rot_array,rot_array_br : rot_array_type; signal Y_delayed : std_logic_vector(3 downto 0); begin Y_delayed(0) <= Y(0); comp_delay1: delay_shiftreg generic map(2,1) port map(clk,Y(2 downto 1),Y_delayed(2 downto 1)); comp_delay2: delay_shiftreg generic map(1,2) port map(clk,Y(3 downto 3),Y_delayed(3 downto 3)); with Y_delayed(0) select rot_array_br(0) <= X when '0', X(n-2 downto 0) & X(n-1) when others; -- rotate 1 with Y_delayed(2 downto 1) select rot_array_br(1) <= rot_array(0) when "00", rot_array(0)(n-3 downto 0) & rot_array(0)(n-1 downto n-2) when "01", -- rotate 2 rot_array(0)(n-5 downto 0) & rot_array(0)(n-1 downto n-4) when "10", -- rotate 4 rot_array(0)(n-7 downto 0) & rot_array(0)(n-1 downto n-6) when others; -- rotate 6 with Y_delayed(3) select rot_array_br(2) <= rot_array(1) when '0', rot_array(1)(n-9 downto 0) & rot_array(1)(n-1 downto n-8) when others; -- rotate 8 proc_reg: process(clk) begin if rising_edge(clk) then rot_array <= rot_array_br; end if; end process; Z <= rot_array(2); end generate; gen_small_laststage1: if (rot_style = "small") and (include_last_stage='1') generate type rot_array_type is array (2 downto 0) of std_logic_vector(n-1 downto 0); signal rot_array,rot_array_br : rot_array_type; signal Y_delayed : std_logic_vector(4 downto 0); begin Y_delayed(0) <= Y(0); Y_delayed(1) <= Y(1); comp_delay1: delay_shiftreg generic map(2,1) port map(clk,Y(3 downto 2),Y_delayed(3 downto 2)); comp_delay2: delay_shiftreg generic map(1,2) port map(clk,Y(4 downto 4),Y_delayed(4 downto 4)); with Y_delayed(1 downto 0) select rot_array_br(0) <= X when "00", X(n-2 downto 0) & X(n-1) when "01", -- rotate 1 X(n-3 downto 0) & X(n-1 downto n-2) when "10", -- rotate 2 X(n-4 downto 0) & X(n-1 downto n-3) when others; -- rotate 3 with Y_delayed(3 downto 2) select rot_array_br(1) <= rot_array(0) when "00", rot_array(0)(n-5 downto 0) & rot_array(0)(n-1 downto n-4) when "01", -- rotate 4 rot_array(0)(n-9 downto 0) & rot_array(0)(n-1 downto n-8) when "10", -- rotate 8 rot_array(0)(n-13 downto 0) & rot_array(0)(n-1 downto n-12) when others; -- rotate 12 with Y_delayed(4) select rot_array_br(2) <= rot_array(1) when '0', rot_array(1)(n-17 downto 0) & rot_array(1)(n-1 downto n-16) when others; -- rotate 16 proc_reg: process(clk) begin if rising_edge(clk) then rot_array <= rot_array_br; end if; end process; Z <= rot_array(2); end generate; gen_small_laststage0: if (rot_style = "small") and (include_last_stage='0') generate type rot_array_type is array (1 downto 0) of std_logic_vector(n-1 downto 0); signal rot_array,rot_array_br : rot_array_type; signal Y_delayed : std_logic_vector(3 downto 0); begin Y_delayed(0) <= Y(0); Y_delayed(1) <= Y(1); comp_delay1: delay_shiftreg generic map(2,1) port map(clk,Y(3 downto 2),Y_delayed(3 downto 2)); with Y_delayed(1 downto 0) select rot_array_br(0) <= X when "00", X(n-2 downto 0) & X(n-1) when "01", -- rotate 1 X(n-3 downto 0) & X(n-1 downto n-2) when "10", -- rotate 2 X(n-4 downto 0) & X(n-1 downto n-3) when others; -- rotate 3 with Y_delayed(3 downto 2) select rot_array_br(1) <= rot_array(0) when "00", rot_array(0)(n-5 downto 0) & rot_array(0)(n-1 downto n-4) when "01", -- rotate 4 rot_array(0)(n-9 downto 0) & rot_array(0)(n-1 downto n-8) when "10", -- rotate 8 rot_array(0)(n-13 downto 0) & rot_array(0)(n-1 downto n-12) when others; -- rotate 12 proc_reg: process(clk) begin if rising_edge(clk) then rot_array <= rot_array_br; end if; end process; Z <= rot_array(1); end generate; end rotate_shiftreg_arch_Virtex;