Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Tue Nov 28 01:41:39 CET 2006
Subject: [cvs-checkins] MODIFIED: CVSROOT ...
Date: 00/06/11 28:01:41

Added: CVSROOT/VHDL/Using_LbRAMs RC5encrypt.vhd
Log:
Here it is (at last).

In the folder "shared_files" are the files used for most of the configurations

Specific files for specific platforms lies in other folders.

The folder "testing" embed the test benches as well as a python script used to generate test data files (and to help generating code for TB.vhd files).



Using_LbRAMs replace regular shift register by shift registers based on bRAMs.



Currently, the real difference between platforms is the way "long_shiftReg" is implemented (because bRAMS instanciation is different).



Enjoy!

--

Guerric


Revision Changes Path
1.1 CVSROOT/VHDL/Using_LbRAMs/RC5encrypt.vhd

http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/Using_LbRAMs/RC5encrypt.vhd?rev=1.1&content-type=text/x-cvsweb-markup

Index: RC5encrypt.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis
-- Create Date: 31/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

use WORK.CompoPack.all;
use WORK.cstPack.all;

entity RC5encrypt is
port(
clk : in std_logic;
key : in std_logic_vector (3*n-1 downto 0);
Plaintext : in std_logic_vector(2*n-1 downto 0);
ok_P,ok_Q : out std_logic);
end RC5encrypt;

architecture RC5encrypt_arch of RC5encrypt is

type ABStmpLtmp_array_type is array (3*t_cst downto 0) of std_logic_vector(n-1 downto 0);
signal A,B,Stmp,Ltmp : ABStmpLtmp_array_type;
signal B_rot_cmd : std_logic_vector(3*t_cst downto 0);

type S_array_type is array (4*t_cst downto 0) of std_logic_vector(n-1 downto 0);
signal S : S_array_type;

type L_array_type is array (3*t_cst-1+3 downto 0) of std_logic_vector(n-1 downto 0);
signal L : L_array_type;
signal L_rot_cmd : std_logic_vector(3*t_cst-1+3 downto 0);

type PQ_array_type is array (r_cst downto 0) of std_logic_vector(n-1 downto 0);
signal P,Q : PQ_array_type;

begin

-- KeySchedule Blocs init
S(0) <= To_StdLogicVector(S32_cst);
gen_Sinit: for i in 1 to t_cst-1 generate
begin
S(i) <= S(i-1) + To_StdLogicVector(T32_cst);
end generate;

ShRegL0 : delay_shiftreg generic map(n,3) port map(clk,key(n-1 downto 0),L(0));
ShRegL1 : delay_shiftreg generic map(n,delayKeyScheduleBox+3) port map(clk,key(2*n-1 downto n),L(1));
ShRegL2 : delay_shiftreg generic map(n,2*delayKeyScheduleBox+3) port map(clk,key(3*n-1 downto 2*n),L(2));
L_rot_cmd(2 downto 0) <= "000";

A(0) <= (others=>'0');
B(0) <= (others=>'0');
B_rot_cmd(0) <= '0';

-- KeySchedule Blocs
gen_KeySchedMap: for i in 0 to 3*t_cst-1 generate begin -- addition of bRAMs for the L signal KeySchedMap: KeyScheduleBloc port map(clk,A(i),S(i),B(i),L(i),B_rot_cmd(i),L_rot_cmd(i),A(i+1),Stmp(i),B(i+1),Ltmp(i),B_rot_cmd(i+1),L_rot_cmd(i+3)); end generate; gen_KeySchedShReg: for i in 0 to t_cst-1 generate begin KeySchedShRegMap: long_shiftreg generic map(delaySregister,delaySregister) port map(clk,Stmp(2*i),Stmp(2*i+1),S(t_cst+2*i),S(t_cst+2*i+1)); end generate; gen_KeySchedShRegL: for i in 0 to t_cst-1 + (t_cst-2)/2 generate begin KeySchedShRegMap: long_shiftreg generic map(delay_Lout,delay_Lout) port map(clk,Ltmp(2*i),Ltmp(2*i+1),L(2*i+3),L(2*i+1+3)); end generate; ---- gen_KeySchedShReg3: for i in 1 to r_cst generate -- !!! ---- begin -- clearly depends on the difference between the number of pipeline stages in both KeyBloc and EncryptBloc ---- KeySchedShReg3Map: long_shiftreg generic map(offset_delayLastS -(2*i),offset_delayLastS -(2*i+1)) port map(clk,Stmp(2*t_cst+2*i),Stmp(2*t_cst+2*i+1),S(3*t_cst+2*i),S(3*t_cst+2*i+1)); ---- end generate; ---- firstShReg3Map: long_shiftreg generic map(offset_delayLastS+delayRot_keysched+2,offset_delayLastS -1) port map(clk,Stmp(2*t_cst),Stmp(2*t_cst+1),S(3*t_cst),S(3*t_cst+1)); gen_KeySchedShReg3: for i in 1 to t_cst-1 generate begin -- clearly depends on the difference between the number of pipeline stages in both KeyBloc and EncryptBloc S(3*t_cst+i) <= Stmp(2*t_cst+i); end generate; firstShReg3Map: delay_shiftreg generic map(n,delayRot_keysched+3) port map(clk,Stmp(2*t_cst),S(3*t_cst)); -- Encrypt Blocs init add_initEncrypt1: add32 port map(clk,Plaintext(n-1 downto 0),S(3*t_cst),P(0)); add_initEncrypt2: add32 port map(clk,Plaintext(2*n-1 downto n),S(3*t_cst+1),Q(0)); -- Encrypt Blocs gen_EncryptMap: for i in 0 to r_cst-2 generate begin encryptMap: EncryptBloc port map(clk,P(i),Q(i),S(3*t_cst+2+2*i),S(3*t_cst+2+2*i+1),P(i+1),Q(i+1)); end generate; encryptMap_last: EncryptBloc_last port map(clk,P(r_cst-1),Q(r_cst-1),S(3*t_cst+2+2*(r_cst-1)),S(3*t_cst+2+2*(r_cst-1)+1),ok_P,ok_Q); end RC5encrypt_arch;