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From: cvs at opencores.org<cvs@o...>
Date: Tue Nov 28 01:41:40 CET 2006
Subject: [cvs-checkins] MODIFIED: CVSROOT ...
Date: 00/06/11 28:01:41 Added: CVSROOT/VHDL/Virtex4 long_shiftreg.vhd
Log:
Here it is (at last).
In the folder "shared_files" are the files used for most of the configurations
Specific files for specific platforms lies in other folders.
The folder "testing" embed the test benches as well as a python script used to generate test data files (and to help generating code for TB.vhd files).
Using_LbRAMs replace regular shift register by shift registers based on bRAMs.
Currently, the real difference between platforms is the way "long_shiftReg" is implemented (because bRAMS instanciation is different).
Enjoy!
--
Guerric
Revision Changes Path
1.1 CVSROOT/VHDL/Virtex4/long_shiftreg.vhd
http://www.opencores.org/cvsweb.shtml/CVSROOT/VHDL/Virtex4/long_shiftreg.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: long_shiftreg.vhd
===================================================================
----------------------------------------------------------------------------------
-- Univeriste catholique de Louvain
-- UCL DICE/Crypto Group
-- Place du Levant, 3
-- B-1348 Louvain-la-Neuve
-- Belgium
--
-- Guerric Meurice de Dormale
-- Acknowledgment: Alexandre Pitsaer for his work during his MsC. thesis
-- Create Date: 19/10/2006
----------------------------------------------------------------------------------
-- This may freely be used, as long as copyright notices are maintained per BSD licensing
-- Guerric Meurice de Dormale, UCL DICE/Crypto Group, Copyright 2006
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity long_shiftreg is
generic(
depthA : integer := 4; -- depth of shift register A (between 4 and 259)
depthB : integer := 4); -- depth of shift register B (between 4 and 259)
port(
clk : in std_logic;
A_in : in std_logic_vector (31 downto 0);
B_in : in std_logic_vector (31 downto 0);
A_out : out std_logic_vector (31 downto 0);
B_out : out std_logic_vector (31 downto 0));
end long_shiftreg;
architecture long_shiftreg_arch_Virtex4 of long_shiftreg is
constant n : integer := 32;
constant ShRegStyleThreshold : integer := 4;
component delay_shiftreg
generic(
n : integer;
delay : integer);
port(
clk : in std_logic;
sig_in : in std_logic_vector (n-1 downto 0);
sig_out : out std_logic_vector (n-1 downto 0));
end component;
begin
gen_smallShReg: if (depthA < ShRegStyleThreshold) or (depthB < ShRegStyleThreshold) generate
begin
ShRagA: delay_shiftreg generic map(n,depthA) port map(clk,A_in,A_out);
ShRagB: delay_shiftreg generic map(n,depthB) port map(clk,B_in,B_out);
end generate;
gen_bigShReg: if not((depthA < ShRegStyleThreshold) or (depthB < ShRegStyleThreshold)) generate
signal DOA,DOB,DIA,DIB : std_logic_vector(31 downto 0);
signal ADDRA,ADDRB : std_logic_vector(14 downto 0);
begin
DIA <= A_in;
DIB <= B_in;
A_out <= DOA;
B_out <= DOB;
gen_equal_depth: if (depthA = depthB) generate
signal ABcounter : std_logic_vector(8 downto 0):=(others=>'1');
begin
proc_countAB: process(clk)
begin
if rising_edge(clk) then
if (ABcounter(8) = '1') then -- if ABcounter < 0 (2's complement)
ABcounter <= CONV_STD_LOGIC_VECTOR(depthA - 4, 9); -- a -1 is added since the output of bRAM is registred
else
ABcounter <= ABcounter - 1;
end if;
end if;
end process;
ADDRA <= "00" & ABcounter(7 downto 0) & "00000";
ADDRB <= "01" & ABcounter(7 downto 0) & "00000";
end generate;
gen_notequal_depth: if not(depthA = depthB) generate
signal Acounter,Bcounter : std_logic_vector(8 downto 0):=(others=>'1');
begin
proc_countA: process(clk)
begin
if rising_edge(clk) then
if (Acounter(8) = '1') then -- if ABcounter < 0 (2's complement)
Acounter <= CONV_STD_LOGIC_VECTOR(depthA - 4, 9); -- a -1 is added since the output of bRAM is registred
else
Acounter <= Acounter - 1;
end if;
end if;
end process;
proc_countB: process(clk)
begin
if rising_edge(clk) then
if (Bcounter(8) = '1') then -- if ABcounter < 0 (2's complement)
Bcounter <= CONV_STD_LOGIC_VECTOR(depthB - 4, 9); -- a -1 is added since the output of bRAM is registred
else
Bcounter <= Bcounter - 1;
end if;
end if;
end process;
ADDRA <= "00" & Acounter(7 downto 0) & "00000";
ADDRB <= "01" & Bcounter(7 downto 0) & "00000";
end generate;
-- RAMB16: Virtex-4 16k+2k Parity Paramatizable BlockRAM
-- Xilinx HDL Language Template version 8.1i
RAMB16_inst : RAMB16
generic map (
DOA_REG => 1, -- Optional output registers on the A port (0 or 1)
DOB_REG => 1, -- Optional output registers on the B port (0 or 1)
INIT_A => X"000000000", -- Initial values on A output port
INIT_B => X"000000000", -- Initial values on B output port
INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers (TRUE or FALSE)
INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers (TRUE or FALSE)
RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
READ_WIDTH_A => 36, -- Valid values are 1,2,4,9,18 or 36
READ_WIDTH_B => 36, -- Valid values are 1,2,4,9,18 or 36
SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY
-- or "NONE
SRVAL_A => X"000000000", -- Port A ouput value upon SSR assertion
SRVAL_B => X"000000000", -- Port B ouput value upon SSR assertion
WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_WIDTH_A => 36, -- Valid values are 1,2,4,9,18 or 36
WRITE_WIDTH_B => 36) -- Valid values are 1,2,4,9,18 or 36
port map (
CASCADEOUTA => open, -- 1-bit cascade output
CASCADEOUTB => open, -- 1-bit cascade output
DOA => DOA, -- 32-bit A port Data Output
DOB => DOB, -- 32-bit B port Data Output
DOPA => open, -- 4-bit A port Parity Output
DOPB => open, -- 4-bit B port Parity Output
ADDRA => ADDRA, -- 15-bit A port Address Input
ADDRB => ADDRB, -- 15-bit B port Address Input
CASCADEINA => '1', -- 1-bit cascade A input
CASCADEINB => '1', -- 1-bit cascade B input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => DIA, -- 32-bit A port Data Input
DIB => DIB, -- 32-bit B port Data Input
DIPA => "1111", -- 4-bit A port parity Input
DIPB => "1111", -- 4-bit B port parity Input
ENA => '1', -- 1-bit A port Enable Input
ENB => '1', -- 1-bit B port Enable Input
REGCEA => '1', -- 1-bit A port register enable input
REGCEB => '1', -- 1-bit B port register enable input
SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input
SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input
WEA => "1111", -- 4-bit A port Write Enable Input
WEB => "1111" -- 4-bit B port Write Enable Input
);
-- End of RAMB16_inst instantiation
end generate;
end long_shiftreg_arch_Virtex4;
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