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From: cvs at opencores.org<cvs@o...>
Date: Fri Nov 17 18:53:07 CET 2006
Subject: [cvs-checkins] MODIFIED: ethernet_tri_mode ...
Date: 00/06/11 17:18:53

Modified: ethernet_tri_mode/rtl/verilog MAC_rx.v MAC_tx.v reg_int.v
Log:
no message


Revision Changes Path
1.4 ethernet_tri_mode/rtl/verilog/MAC_rx.v

http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/rtl/verilog/MAC_rx.v.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: MAC_rx.v
===================================================================
RCS file: /cvsroot/maverickist/ethernet_tri_mode/rtl/verilog/MAC_rx.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- MAC_rx.v 19 Jan 2006 14:07:52 -0000 1.3
+++ MAC_rx.v 17 Nov 2006 17:53:07 -0000 1.4
@@ -39,6 +39,9 @@
// CVS Revision History
//
// $Log: MAC_rx.v,v $
+// Revision 1.4 2006/11/17 17:53:07 maverickist
+// no message
+//
// Revision 1.3 2006/01/19 14:07:52 maverickist
// verification is complete.
//
@@ -103,8 +106,8 @@
wire broadcast_ptr ;
wire broadcast_drop ;
//flow_control signals
-wire [15:0] pause_quanta ;
-wire pause_quanta_val ;
+//wire [15:0] pause_quanta ;
+//wire pause_quanta_val ;
//MAC_rx_ctrl interface
wire [7:0] Fifo_data ;
wire Fifo_data_en ;



1.4 ethernet_tri_mode/rtl/verilog/MAC_tx.v

http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/rtl/verilog/MAC_tx.v.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: MAC_tx.v
===================================================================
RCS file: /cvsroot/maverickist/ethernet_tri_mode/rtl/verilog/MAC_tx.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- MAC_tx.v 19 Jan 2006 14:07:53 -0000 1.3
+++ MAC_tx.v 17 Nov 2006 17:53:07 -0000 1.4
@@ -39,6 +39,9 @@
// CVS Revision History
//
// $Log: MAC_tx.v,v $
+// Revision 1.4 2006/11/17 17:53:07 maverickist
+// no message
+//
// Revision 1.3 2006/01/19 14:07:53 maverickist
// verification is complete.
//
@@ -86,7 +89,7 @@
input xon_cpu ,
//MAC_rx_flow ,
input [15:0] pause_quanta ,
-input pause_quanta_val ,
+input pause_quanta_val
);
//******************************************************************************
//internal signals



1.4 ethernet_tri_mode/rtl/verilog/reg_int.v

http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/rtl/verilog/reg_int.v.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: reg_int.v
===================================================================
RCS file: /cvsroot/maverickist/ethernet_tri_mode/rtl/verilog/reg_int.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- reg_int.v 25 Jun 2006 04:58:56 -0000 1.3
+++ reg_int.v 17 Nov 2006 17:53:07 -0000 1.4
@@ -59,7 +59,7 @@
input [15:0] Prsd ,// Read Status Data (data read from the PHY)
input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
-input UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
+input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data
); RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in);