Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Fri Nov 17 18:53:07 CET 2006
Subject: [cvs-checkins] MODIFIED: ethernet_tri_mode ...
Date: 00/06/11 17:18:53

Modified: ethernet_tri_mode/bench/verilog Phy_sim.v User_int_sim.v
Log:
no message


Revision Changes Path
1.3 ethernet_tri_mode/bench/verilog/Phy_sim.v

http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/bench/verilog/Phy_sim.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: Phy_sim.v
===================================================================
RCS file: /cvsroot/maverickist/ethernet_tri_mode/bench/verilog/Phy_sim.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- Phy_sim.v 19 Jan 2006 14:07:50 -0000 1.2
+++ Phy_sim.v 17 Nov 2006 17:53:07 -0000 1.3
@@ -39,6 +39,9 @@
// CVS Revision History
//
// $Log: Phy_sim.v,v $
+// Revision 1.3 2006/11/17 17:53:07 maverickist
+// no message
+//
// Revision 1.2 2006/01/19 14:07:50 maverickist
// verification is complete.
//
@@ -72,8 +75,8 @@
//////////////////////////////////////////////////////////////////////
reg Clk_25m ;//used for 100 Mbps mode
reg Clk_2_5m ;//used for 10 Mbps mode
-wire Rx_clk ;
-wire Tx_clk ;//used only in MII mode
+//wire Rx_clk ;
+//wire Tx_clk ;//used only in MII mode
//////////////////////////////////////////////////////////////////////
always
begin



1.3 ethernet_tri_mode/bench/verilog/User_int_sim.v

http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/bench/verilog/User_int_sim.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: User_int_sim.v
===================================================================
RCS file: /cvsroot/maverickist/ethernet_tri_mode/bench/verilog/User_int_sim.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- User_int_sim.v 19 Jan 2006 14:07:50 -0000 1.2
+++ User_int_sim.v 17 Nov 2006 17:53:07 -0000 1.3
@@ -39,6 +39,9 @@
// CVS Revision History
//
// $Log: User_int_sim.v,v $
+// Revision 1.3 2006/11/17 17:53:07 maverickist
+// no message
+//
// Revision 1.2 2006/01/19 14:07:50 maverickist
// verification is complete.
//
@@ -49,25 +52,45 @@
// no message
//
module User_int_sim (
-input Reset ,
-input Clk_user ,
-input CPU_init_end ,
+Reset ,
+Clk_user ,
+CPU_init_end ,
+//user inputerface ,
+Rx_mac_ra ,
+Rx_mac_rd ,
+Rx_mac_data ,
+Rx_mac_BE ,
+Rx_mac_pa ,
+Rx_mac_sop ,
+Rx_mac_eop ,
+//user inputerface ,
+Tx_mac_wa ,
+Tx_mac_wr ,
+Tx_mac_data ,
+Tx_mac_BE ,
+Tx_mac_sop ,
+Tx_mac_eop
+
+);
+input Reset ;
+input Clk_user ;
+input CPU_init_end ;
//user inputerface
-input Rx_mac_ra ,
-output Rx_mac_rd , -input [31:0] Rx_mac_data , -input [1:0] Rx_mac_BE , -input Rx_mac_pa , -input Rx_mac_sop , -input Rx_mac_eop , +input Rx_mac_ra ; +output Rx_mac_rd ; +input [31:0] Rx_mac_data ; +input [1:0] Rx_mac_BE ; +input Rx_mac_pa ; +input Rx_mac_sop ; +input Rx_mac_eop ; //user inputerface -input Tx_mac_wa , -output Tx_mac_wr , -output [31:0] Tx_mac_data , -output [1:0] Tx_mac_BE ,//big endian -output Tx_mac_sop , -output Tx_mac_eop -); +input Tx_mac_wa ; +output Tx_mac_wr ; +output [31:0] Tx_mac_data ; +output [1:0] Tx_mac_BE ;//big endian +output Tx_mac_sop ; +output Tx_mac_eop ; + ////////////////////////////////////////////////////////////////////// // inputernal signals //////////////////////////////////////////////////////////////////////