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Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Aug 18 16:29:35 CEST 2006
Subject: [cvs-checkins] MODIFIED: dirac ...
Date: 00/06/08 18:16:29 Modified: dirac/src/encoder ARITHMETICCODER.vhd arithmeticcoder.prj
Log:
Complete implementation of adaptive arithmetic coding, suitable for Dirac 0.5.3
Revision Changes Path
1.3 dirac/src/encoder/ARITHMETICCODER.vhd
http://www.opencores.org/cvsweb.shtml/dirac/src/encoder/ARITHMETICCODER.vhd.diff?r1=1.2&r2=1.3
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ARITHMETICCODER.vhd
===================================================================
RCS file: /cvsroot/petebleackley/dirac/src/encoder/ARITHMETICCODER.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- ARITHMETICCODER.vhd 27 May 2005 16:00:30 -0000 1.2
+++ ARITHMETICCODER.vhd 18 Aug 2006 14:29:33 -0000 1.3
@@ -1,38 +1,37 @@
-- ***** BEGIN LICENSE BLOCK *****
--
--- $Id: ARITHMETICCODER.vhd,v 1.2 2005/05/27 16:00:30 petebleackley Exp $ $Name: $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
+--
+-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
+--
+-- The contents of this file are subject to the Mozilla Public License
+-- Version 1.1 (the "License"); you may not use this file except in compliance
+-- with the License. You may obtain a copy of the License at
+-- http://www.mozilla.org/MPL/
+--
+-- Software distributed under the License is distributed on an "AS IS" basis,
+-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- the specific language governing rights and limitations under the License.
+--
+-- The Original Code is BBC Research and Development code.
+--
+-- The Initial Developer of the Original Code is the British Broadcasting
+-- Corporation.
+-- Portions created by the Initial Developer are Copyright (C) 2006.
+-- All Rights Reserved.
+--
+-- Contributor(s): Peter Bleackley (Original author)
+--
+-- Alternatively, the contents of this file may be used under the terms of
+-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- the GPL or the LGPL are applicable instead of those above. If you wish to
+-- allow use of your version of this file only under the terms of the either
+-- the GPL or LGPL and not to allow others to use your version of this file
+-- under the MPL, indicate your decision by deleting the provisions above
+-- and replace them with the notice and other provisions required by the GPL
+-- or LGPL. If you do not delete the provisions above, a recipient may use
+-- your version of this file under the terms of any one of the MPL, the GPL
+-- or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
library IEEE;
@@ -50,10 +49,13 @@
DATA_IN : in std_logic;
CONTEXT_ENABLE : in std_logic;
CONTEXT_IN : in std_logic_vector (5 downto 0);
+ HALVECOUNTS_IN : in std_logic;
+ FLUSH : in std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
SENDING : out std_logic;
- DATA_OUT : out std_logic);
+ DATA_OUT : out std_logic;
+ FLUSH_COMPLETE : out std_logic);
end ARITHMETICCODER;
architecture RTL of ARITHMETICCODER is
@@ -121,12 +123,18 @@
end component INPUT_CONTROL;
component CONTEXT_MANAGER
port ( CONTEXT_NUMBER : in std_logic_vector(5 downto 0);
+ SET : in std_logic;
+ UPDATE : in std_logic;
+ DATA_IN : in std_logic;
+ HALVECOUNTS : in std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
- PROB : out std_logic_vector(9 downto 0));
+ PROB : out std_logic_vector(9 downto 0);
+ READY : out std_logic);
end component CONTEXT_MANAGER;
signal HIGH_SET : std_logic;
signal LOW_SET : std_logic;
+ signal TRIGGER_SHIFT : std_logic;
signal SHIFT_ALL : std_logic;
signal DIFFERENCE_SHIFT_ALL : std_logic;
signal SHIFT_MOST : std_logic;
@@ -159,7 +167,22 @@
signal BUFFERCONTEXT : std_logic;
signal DATA_IN2 : std_logic_vector(0 downto 0);
signal BUFFERED_DATA2 : std_logic_vector(0 downto 0);
-
+ signal CONTEXT_BUFFER_DATA_IN : std_logic_vector(7 downto 0);
+ signal CONTEXT_BUFFER_DATA_OUT : std_logic_vector(7 downto 0);
+-- signal LAST_FIVE_TRIGGERS : std_logic_vector(4 downto 0);
+ signal HALVECOUNTS : std_logic;
+ signal BUFFERED_FLUSH : std_logic;
+ signal FLUSH_ENCODER : std_logic;
+ signal SWITCHED_DATA : std_logic;
+ signal CONVERGED : std_logic;
+ signal INCREMENT_FOLLOW : std_logic;
+ signal ALLOWHALVING : std_logic;
+ signal RELEASE_CONTEXT : std_logic;
+-- signal FETCH_FLUSH : std_logic;
+ signal DEMAND_CONTEXT : std_logic;
+ signal LOCK : std_logic;
+ signal DEMAND_DATA : std_logic;
+ signal HOLDCONTEXT : std_logic;
begin
-- input buffering
INBUFFER: INPUT_CONTROL
@@ -167,7 +190,7 @@
port map(ENABLE => ENABLE,
DATA_IN => DATA_IN2,
BUFFER_CONTROL => BUFFER_INPUT,
- DEMAND => ARITHMETIC_UNIT_DATA_LOAD,
+ DEMAND => DEMAND_DATA,
RESET => RESET,
CLOCK => CLOCK,
SENDING => DATA_AVAILABLE,
@@ -175,17 +198,28 @@
DATA_IN2(0) <= DATA_IN;
BUFFERED_DATA <= BUFFERED_DATA2(0);
+ DEMAND_DATA <= ARITHMETIC_UNIT_DATA_LOAD and not LOCK;
CONTEXT_BUFFER: INPUT_CONTROL
- generic map(WIDTH => 6)
+ generic map(WIDTH => 8)
port map(ENABLE => CONTEXT_ENABLE,
- DATA_IN => CONTEXT_IN,
+ DATA_IN => CONTEXT_BUFFER_DATA_IN,
BUFFER_CONTROL => BUFFERCONTEXT,
- DEMAND => DATA_LOAD,
+ DEMAND => DEMAND_CONTEXT,
RESET => RESET,
CLOCK => CLOCK,
SENDING => NEWCONTEXT,
- DATA_OUT => CONTEXT_SELECT);
+ DATA_OUT => CONTEXT_BUFFER_DATA_OUT);
+
+ CONTEXT_BUFFER_DATA_IN <= (CONTEXT_IN & HALVECOUNTS_IN & FLUSH);
+
+ CONTEXT_SELECT <= CONTEXT_BUFFER_DATA_OUT(7 downto 2);
+ HALVECOUNTS <= CONTEXT_BUFFER_DATA_OUT(1) and ALLOWHALVING;
+ BUFFERED_FLUSH <= CONTEXT_BUFFER_DATA_OUT(0) and CONVERGENCE_TEST and (CONVERGED nor SHIFT_MOST) and not LOCK;
+
+
+
+
-- Specify the registers
HIGH: LIMIT_REGISTER
generic map(CONST => '1')
@@ -240,33 +274,36 @@
HIGH_SECONDBIT => HIGH_OUT(14),
LOW_SECONDBIT => LOW_OUT(14),
CHECK => CONVERGENCE_TEST,
- TRIGGER_OUTPUT => TRIGGER_OUTPUT,
+ TRIGGER_OUTPUT => CONVERGED,
TRIGGER_FOLLOW => SHIFT_MOST);
+ TRIGGER_OUTPUT <= CONVERGED or FLUSH_ENCODER;
--The Follow Counter
FC: FOLLOW_COUNTER
- port map( INCREMENT => SHIFT_MOST,
+ port map( INCREMENT => INCREMENT_FOLLOW,
TEST => FOLLOW_COUNTER_TEST,
RESET => RESET,
CLOCK => CLOCK,
OUTPUT => FOLLOW);
-
+ INCREMENT_FOLLOW <= SHIFT_MOST or BUFFERED_FLUSH;
--The output unit
OUTPUT: OUTPUT_UNIT
port map(ENABLE => TRIGGER_OUTPUT,
- DATA => HIGH_OUT(15),
+ DATA => SWITCHED_DATA,
FOLLOW => FOLLOW,
RESET => RESET,
CLOCK => CLOCK,
SENDING => OUTPUT_ACTIVE,
DATA_OUT => DATA_OUT,
FOLLOW_COUNTER_TEST => FOLLOW_COUNTER_TEST,
- SHIFT => SHIFT_ALL);
+ SHIFT => TRIGGER_SHIFT);
SENDING <= OUTPUT_ACTIVE;
+ SHIFT_ALL <= TRIGGER_SHIFT and not FLUSH_ENCODER;
+
-- Input logic
DATA_LOAD <= DATA_AVAILABLE and ARITHMETIC_UNIT_DATA_LOAD;
@@ -274,6 +311,15 @@
ZERO_INPUT <= not BUFFERED_DATA;
LOW_SET <= BUFFERED_DATA and DATA_LOAD;
+FLUSH_SWITCH : process (FLUSH_ENCODER,LOW_OUT,HIGH_OUT)
+begin
+ if FLUSH_ENCODER = '1' then
+ SWITCHED_DATA <= LOW_OUT(14);
+ else
+ SWITCHED_DATA <= HIGH_OUT(15);
+ end if;
+end process FLUSH_SWITCH;
+
-- Control logic for DIFFERENCE register
DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST;
@@ -314,25 +360,97 @@
PROBABILITY : CONTEXT_MANAGER
port map(CONTEXT_NUMBER => CONTEXT_SELECT,
+ SET => NEWCONTEXT,
+ UPDATE => DATA_LOAD,
+ DATA_IN => BUFFERED_DATA,
+ HALVECOUNTS => HALVECOUNTS,
RESET => RESET,
CLOCK => CLOCK,
- PROB => PROB);
+ PROB => PROB,
+ READY => PROB_AVAILABLE);
-ISPROBAVAILABLE : process (CLOCK)
- begin
- if (CLOCK'event and CLOCK = '1') then
- if (RESET = '1' or (DATA_LOAD = '1' and NEWCONTEXT = '0')) then
- PROB_AVAILABLE <= '0';
- elsif (NEWCONTEXT = '1') then
- PROB_AVAILABLE <= '1';
+
+
+FLUSH_CONTROL : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK = '1' then
+ if RESET = '1' then
+ FLUSH_ENCODER <= '0';
+ elsif BUFFERED_FLUSH = '1' then
+ FLUSH_ENCODER <= '1';
+ elsif TRIGGER_SHIFT = '1' then
+ FLUSH_ENCODER <= '0';
end if;
end if;
-end process ISPROBAVAILABLE;
+end process FLUSH_CONTROL;
- BUFFERCONTEXT <= PROB_AVAILABLE and not ARITHMETIC_UNIT_DATA_LOAD;
+FLUSH_COMPLETE <= FLUSH_ENCODER and TRIGGER_SHIFT;
---
+LIMITHALVING : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ if RESET='1' then
+ ALLOWHALVING <= '1';
+ else
+ ALLOWHALVING <= not CONTEXT_BUFFER_DATA_OUT(1);
+ end if;
+ end if;
+end process LIMITHALVING;
-end RTL;
+RELEASE_CONTEXT <= RESET or DEMAND_CONTEXT;
+
+CONTEXTS_SHOULD_BE_BUFFERED : process (RELEASE_CONTEXT,CLOCK)
+begin
+ if CLOCK'event and CLOCK = '1' then
+ if NEWCONTEXT = '1' then
+ HOLDCONTEXT <= '1';
+ elsif RELEASE_CONTEXT = '1' then
+ HOLDCONTEXT <= '0';
+ end if;
+ end if;
+end process CONTEXTS_SHOULD_BE_BUFFERED;
+
+BUFFERCONTEXT <= HOLDCONTEXT and not RELEASE_CONTEXT;
+
+--STORE_TRIGGERS : process (CLOCK)
+--begin
+-- if CLOCK'event and CLOCK='1' then
+-- if RESET='1' then
+-- LAST_FIVE_TRIGGERS <= "11111";
+-- else
+-- LAST_FIVE_TRIGGERS <= LAST_FIVE_TRIGGERS(3 downto 0) & (DATA_AVAILABLE or OUTPUT_ACTIVE or DIFFERENCE_SHIFT_ALL);
+-- end if;
+-- end if;
+--end process STORE_TRIGGERS;
+
+--GET_FLUSH_SIGNAL : process (LAST_FIVE_TRIGGERS)
+--begin
+-- if LAST_FIVE_TRIGGERS = "00000" then
+-- FETCH_FLUSH <= '1';
+-- else
+-- FETCH_FLUSH <= '0';
+-- end if;
+--end process GET_FLUSH_SIGNAL;
+
+LOCK_ENCODER : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ if RESET = '1' then
+ LOCK <= '0';
+ elsif BUFFERED_FLUSH='1' then
+ LOCK <= '1';
+ end if;
+ end if;
+end process LOCK_ENCODER;
+DEMAND_CONTEXT <= DATA_LOAD; -- or FETCH_FLUSH;--DATA_LOAD or FETCH_FLUSH or AFTER_RESET;
+--DELAY_RESET: process (CLOCK)
+--begin
+-- if CLOCK'event and CLOCK='1' then
+-- AFTER_RESET <= RESET;
+-- end if;
+--end process DELAY_RESET;
+--
+
+end RTL;
1.3 dirac/src/encoder/arithmeticcoder.prj
http://www.opencores.org/cvsweb.shtml/dirac/src/encoder/arithmeticcoder.prj.diff?r1=1.2&r2=1.3
(In the diff below, changes in quantity of whitespace are not shown.)
Index: arithmeticcoder.prj
===================================================================
RCS file: /cvsroot/petebleackley/dirac/src/encoder/arithmeticcoder.prj,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- arithmeticcoder.prj 27 May 2005 16:00:30 -0000 1.2
+++ arithmeticcoder.prj 18 Aug 2006 14:29:33 -0000 1.3
@@ -1,6 +1,9 @@
vhdl work ../common/FIFO.vhd
vhdl work ../common/INPUT_CONTROL.vhd
vhdl work LIMIT_REGISTER.vhd
+vhdl work ../common/HALVING_MANAGER.vhd
+vhdl work ../common/UPDATER.vhd
+vhdl work ../common/Divider.vhd
vhdl work ../common/CONTEXT_MANAGER.vhd
vhdl work ../common/ARITHMETIC_UNIT.vhd
vhdl work ../common/CONVERGENCE_CHECK.vhd
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