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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Fri Aug 18 16:29:33 CEST 2006
    Subject: [cvs-checkins] MODIFIED: dirac ...
    Top
    Date: 00/06/08 18:16:29

    Modified: dirac/src/common CONTEXT_MANAGER.vhd context_manager.prj
    Added: dirac/src/common Divider.vhd HALVING_MANAGER.vhd UPDATER.vhd
    Log:
    Complete implementation of adaptive arithmetic coding, suitable for Dirac 0.5.3


    Revision Changes Path
    1.2 dirac/src/common/CONTEXT_MANAGER.vhd

    http://www.opencores.org/cvsweb.shtml/dirac/src/common/CONTEXT_MANAGER.vhd.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: CONTEXT_MANAGER.vhd
    ===================================================================
    RCS file: /cvsroot/petebleackley/dirac/src/common/CONTEXT_MANAGER.vhd,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- CONTEXT_MANAGER.vhd 27 May 2005 16:00:28 -0000 1.1
    +++ CONTEXT_MANAGER.vhd 18 Aug 2006 14:29:32 -0000 1.2
    @@ -1,6 +1,6 @@
    -- ***** BEGIN LICENSE BLOCK *****
    --
    --- $Id: CONTEXT_MANAGER.vhd,v 1.1 2005/05/27 16:00:28 petebleackley Exp $ $Name: $
    +-- $Id: CONTEXT_MANAGER.vhd,v 1.2 2006/08/18 14:29:32 petebleackley Exp $ $Name: $
    -- *
    -- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
    -- *
    @@ -47,31 +47,172 @@

    entity CONTEXT_MANAGER is
    Port ( CONTEXT_NUMBER : in std_logic_vector(5 downto 0);
    + SET : in std_logic;
    + UPDATE : in std_logic;
    + DATA_IN : in std_logic;
    + HALVECOUNTS : in std_logic;
    RESET : in std_logic;
    CLOCK : in std_logic;
    - PROB : out std_logic_vector(9 downto 0));
    + PROB : out std_logic_vector(9 downto 0);
    + READY : out std_logic);
    end CONTEXT_MANAGER;

    architecture RTL of CONTEXT_MANAGER is
    - type MATRIX is array (63 downto 0) of std_logic_vector(9 downto 0);
    - signal PROBABILITY : MATRIX := ("1111111111","0011011010","1111000000",
    - "1100110000","0111110000","1001111100","0000010000","0000110011","1100110011",
    - "1101110111","0110011010","1000111000","0000001010","0000110011","1000110011",
    - "0101011011","1110000000","0100111101","1000001010","1110011011","0000001010",
    - "0101111000","1111000000","1111001101","0111001101","1101011100","0111110110",
    - "0110000011","1111110110","0101000110","1110011010","1110101110","0111000011",
    - "0110010110","1111001101","0011001101","1001100110","1100100101","0001100110",
    - "1110011010","0100110011","1111001101","0111001101","0011101111","1110011010",
    - "1111100011","0011001101","0101000000","1110000000","0011000000","1100000000",
    - "0110101011","1010101011","1110011010","0110011010","1001110010","0101010101",
    - "1000111001","0101010101","1100110011","0110011010","0100000000","1100000000",
    - "1000000000");
    +
    + type MATRIX is array (45 downto 0) of std_logic_vector(19 downto 0);
    + signal PROBABILITY : MATRIX;
    + constant HALF : std_logic_vector(19 downto 0) := "00000000010000000010";
    + signal FRACTION : std_logic_vector(19 downto 0);
    + signal FRACTION2 : std_logic_vector(19 downto 0);
    + signal RESET_FLAGS : std_logic_vector (63 downto 0);
    + signal NEWPROB : std_logic_vector(19 downto 0);
    + signal RATIO : std_logic_vector(19 downto 0);
    + signal UPDATE_PROB : std_logic;
    + signal PROB_CHANGED : std_logic;
    + signal LOAD_DATA : std_logic;
    + signal OLD_CONTEXT : std_logic_vector (5 downto 0);
    + signal READ_ADDRESS : std_logic_vector (5 downto 0);
    + signal DATA_FETCHED : std_logic;
    + signal CONTEXT_VALID : std_logic;
    + signal DATA_READY : std_logic_vector (1 downto 0);
    +
    + component DIVIDER
    + port ( NUMERATOR : in std_logic_vector(9 downto 0);
    + DENOMINATOR : in std_logic_vector(9 downto 0);
    + RESET : in std_logic;
    + CLOCK : in std_logic;
    + QUOTIENT : out std_logic_vector(9 downto 0));
    + end component DIVIDER;
    + component UPDATER
    + port ( NUMERATOR : in std_logic_vector(9 downto 0);
    + DENOMINATOR : in std_logic_vector(9 downto 0);
    + ENABLE : in std_logic;
    + DATA_IN : in std_logic;
    + RESET : in std_logic;
    + CLOCK : in std_logic;
    + NUMERATOR_OUT : out std_logic_vector(9 downto 0);
    + DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
    + UPDATE : out std_logic);
    + end component UPDATER;
    + component HALVING_MANAGER
    + port ( TRIGGER_HALVING : in std_logic;
    + INPUT_READY : in std_logic;
    + NUMERATOR_IN : in std_logic_vector(9 downto 0);
    + DENOMINATOR_IN : in std_logic_vector(9 downto 0);
    + CONTEXT : in std_logic_vector(5 downto 0);
    + RESET : in std_logic; + CLOCK : in std_logic; + NUMERATOR_OUT : out std_logic_vector(9 downto 0); + DENOMINATOR_OUT : out std_logic_vector(9 downto 0); + OUTPUT_READY : out std_logic); + end component HALVING_MANAGER; + +begin + +FLAGS: process(CLOCK) +begin + if (CLOCK'event and CLOCK='1') then + if (RESET='1') then + RESET_FLAGS <= (others => '1'); + elsif LOAD_DATA = '1' then + RESET_FLAGS(conv_integer(OLD_CONTEXT)) <= '0'; + end if; + end if; +end process FLAGS; + +LOAD_DATA <= UPDATE_PROB and UPDATE; + + +MEMORY: process(CLOCK) +begin + if (CLOCK'event and CLOCK='1') then + if SET='1' then + READ_ADDRESS <= CONTEXT_NUMBER; + end if; + if (LOAD_DATA = '1') then + PROBABILITY(conv_integer(OLD_CONTEXT)) <= NEWPROB; + end if; + end if; +end process MEMORY; +RATIO <= PROBABILITY(conv_integer(READ_ADDRESS)); + +CHOOSE_FRACTION : process (READ_ADDRESS,RESET_FLAGS,RATIO) +begin + if (RESET_FLAGS(conv_integer(READ_ADDRESS))='1') then + FRACTION <= HALF; + else + FRACTION <= RATIO; + end if; +end process CHOOSE_FRACTION; + + +DIVISION : DIVIDER + port map (NUMERATOR => FRACTION2(19 downto 10), + DENOMINATOR => FRACTION2(9 downto 0), + RESET => RESET, + CLOCK => CLOCK, + QUOTIENT => PROB); + +PROBUPDATE : UPDATER + port map (NUMERATOR => FRACTION2(19 downto 10), + DENOMINATOR => FRACTION2(9 downto 0), + ENABLE => PROB_CHANGED, + DATA_IN => DATA_IN, + RESET => RESET, + CLOCK => CLOCK, + NUMERATOR_OUT => NEWPROB(19 downto 10), + DENOMINATOR_OUT => NEWPROB(9 downto 0), + UPDATE => UPDATE_PROB); + +REFRESH: HALVING_MANAGER + port map (TRIGGER_HALVING => HALVECOUNTS, + INPUT_READY => DATA_FETCHED, + NUMERATOR_IN => FRACTION(19 downto 10), + DENOMINATOR_IN => FRACTION(9 downto 0), + CONTEXT => CONTEXT_NUMBER, + RESET => RESET, + CLOCK => CLOCK, + NUMERATOR_OUT => FRACTION2(19 downto 10), + DENOMINATOR_OUT => FRACTION2(9 downto 0), + OUTPUT_READY => PROB_CHANGED); + + +DELAY_CONTEXT : process (CLOCK) begin - OUTPUT : process (CLOCK) - begin if CLOCK'event and CLOCK = '1' then - PROB <= PROBABILITY(conv_integer(CONTEXT_NUMBER)); + OLD_CONTEXT <= CONTEXT_NUMBER; end if; - end process OUTPUT; +end process DELAY_CONTEXT; + + +IS_DATA_READY : process (CLOCK) +begin + if CLOCK'event and CLOCK='1' then + if RESET='1' then + DATA_READY <= "00"; + else + DATA_READY <= DATA_READY(0) & PROB_CHANGED; + end if; + end if; +end process IS_DATA_READY; + +CONTEXT_LOADED : process (CLOCK) +begin + if CLOCK'event and CLOCK='1' then + if RESET='1' then + CONTEXT_VALID <= '0'; + elsif SET = '1' then + CONTEXT_VALID <= '1'; + elsif UPDATE = '1' then + CONTEXT_VALID <= '0'; + end if; + end if; +end process CONTEXT_LOADED; + +DATA_FETCHED <= CONTEXT_VALID and not SET; + + +READY <= (DATA_READY(1) and DATA_READY (0));-- and not SET; + end RTL; 1.2 dirac/src/common/context_manager.prj http://www.opencores.org/cvsweb.shtml/dirac/src/common/context_manager.prj.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: context_manager.prj =================================================================== RCS file: /cvsroot/petebleackley/dirac/src/common/context_manager.prj,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- context_manager.prj 27 May 2005 16:00:28 -0000 1.1 +++ context_manager.prj 18 Aug 2006 14:29:32 -0000 1.2 @@ -1 +1,4 @@ +vhdl work HALVING_MANAGER.vhd +vhdl work UPDATER.vhd +vhdl work DIVIDER.vhd vhdl work CONTEXT_MANAGER.vhd 1.1 dirac/src/common/Divider.vhd http://www.opencores.org/cvsweb.shtml/dirac/src/common/Divider.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: Divider.vhd =================================================================== -- ***** BEGIN LICENSE BLOCK ***** -- -- -- Version: MPL 1.1/GPL 2.0/LGPL 2.1 -- -- The contents of this file are subject to the Mozilla Public License -- Version 1.1 (the "License"); you may not use this file except in compliance -- with the License. You may obtain a copy of the License at -- http://www.mozilla.org/MPL/ -- -- Software distributed under the License is distributed on an "AS IS" basis, -- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for -- the specific language governing rights and limitations under the License. -- -- The Original Code is BBC Research and Development code. -- -- The Initial Developer of the Original Code is the British Broadcasting -- Corporation. -- Portions created by the Initial Developer are Copyright (C) 2006. -- All Rights Reserved. -- -- Contributor(s): Peter Bleackley (Original author) -- -- Alternatively, the contents of this file may be used under the terms of -- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser -- Public License Version 2.1 (the "LGPL"), in which case the provisions of -- the GPL or the LGPL are applicable instead of those above. If you wish to -- allow use of your version of this file only under the terms of the either -- the GPL or LGPL and not to allow others to use your version of this file -- under the MPL, indicate your decision by deleting the provisions above -- and replace them with the notice and other provisions required by the GPL -- or LGPL. If you do not delete the provisions above, a recipient may use -- your version of this file under the terms of any one of the MPL, the GPL -- or the LGPL. -- * ***** END LICENSE BLOCK ***** */ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity Divider is Port ( NUMERATOR : in std_logic_vector(9 downto 0); DENOMINATOR : in std_logic_vector(9 downto 0); RESET : in std_logic; CLOCK : in std_logic; QUOTIENT : out std_logic_vector(9 downto 0)); end Divider; architecture RTL of Divider is signal NUMERATOR2 : std_logic_vector(9 downto 0); signal DENOMINATOR2 : std_logic_vector( 9 downto 0); signal RECIPROCAL : std_logic_vector(31 downto 0); signal PRODUCT1 : std_logic_vector(25 downto 0); signal PRODUCT2 : std_logic_vector(25 downto 0); signal TOTAL : std_logic_vector(41 downto 0); signal INDEX : std_logic_vector (9 downto 0); type ROM is array (1021 downto 0) of std_logic_vector(31 downto 0); constant LUT : ROM := ("00000000010000000001000000000100", "00000000010000000010000000010000", "00000000010000000011000000100100", "00000000010000000100000001000000", "00000000010000000101000001100100", "00000000010000000110000010010000", "00000000010000000111000011000101", "00000000010000001000000100000010", "00000000010000001001000101000110", "00000000010000001010000110010011", "00000000010000001011000111101001", "00000000010000001100001001000110", "00000000010000001101001010101100", "00000000010000001110001100011010", "00000000010000001111001110010001", "00000000010000010000010000010000", "00000000010000010001010010010111", "00000000010000010010010100100111", "00000000010000010011010110111111", "00000000010000010100011001011111", "00000000010000010101011100001000", "00000000010000010110011110111010", "00000000010000010111100001110100", "00000000010000011000100100110111", "00000000010000011001101000000010", "00000000010000011010101011010110", "00000000010000011011101110110010", "00000000010000011100110010011000", "00000000010000011101110110000110", "00000000010000011110111001111100", "00000000010000011111111101111100", "00000000010000100001000010000100", "00000000010000100010000110010101", "00000000010000100011001010101110", "00000000010000100100001111010001", "00000000010000100101010011111100", "00000000010000100110011000110001", "00000000010000100111011101101110", "00000000010000101000100010110100", "00000000010000101001101000000100", "00000000010000101010101101011100", "00000000010000101011110010111101", "00000000010000101100111000101000", "00000000010000101101111110011011", "00000000010000101111000100011000", "00000000010000110000001010011110", "00000000010000110001010000101101", "00000000010000110010010111000101", "00000000010000110011011101100110", "00000000010000110100100100010001", "00000000010000110101101011000101", "00000000010000110110110010000010", "00000000010000110111111001001001", "00000000010000111001000000011001", "00000000010000111010000111110010", "00000000010000111011001111010101", "00000000010000111100010111000010", "00000000010000111101011110110111", "00000000010000111110100110110111", "00000000010000111111101111000000", "00000000010001000000110111010010", "00000000010001000001111111101110", "00000000010001000011001000010100", "00000000010001000100010001000100", "00000000010001000101011001111101", "00000000010001000110100011000000", "00000000010001000111101100001101", "00000000010001001000110101100011", "00000000010001001001111111000011", "00000000010001001011001000101110", "00000000010001001100010010100010", "00000000010001001101011100100000", "00000000010001001110100110101000", "00000000010001001111110000111010", "00000000010001010000111011010110", "00000000010001010010000101111100", "00000000010001010011010000101100", "00000000010001010100011011100110", "00000000010001010101100110101010", "00000000010001010110110001111001", "00000000010001010111111101010010", "00000000010001011001001000110101", "00000000010001011010010100100010", "00000000010001011011100000011010", "00000000010001011100101100011100", "00000000010001011101111000101000", "00000000010001011111000100111111", "00000000010001100000010001100000", "00000000010001100001011110001011", "00000000010001100010101011000010", "00000000010001100011111000000010", "00000000010001100101000101001110", "00000000010001100110010010100011", "00000000010001100111100000000100", "00000000010001101000101101101111", "00000000010001101001111011100101", "00000000010001101011001001100110", "00000000010001101100010111110001", "00000000010001101101100110000111", "00000000010001101110110100101001", "00000000010001110000000011010101", "00000000010001110001010010001011", "00000000010001110010100001001101", "00000000010001110011110000011010", "00000000010001110100111111110010", "00000000010001110110001111010101", "00000000010001110111011111000011", "00000000010001111000101110111100", "00000000010001111001111111000001", "00000000010001111011001111010000", "00000000010001111100011111101011", "00000000010001111101110000010001", "00000000010001111111000001000011", "00000000010010000000010010000000", "00000000010010000001100011001000", "00000000010010000010110100011100", "00000000010010000100000101111011", "00000000010010000101010111100110", "00000000010010000110101001011100", "00000000010010000111111011011110", "00000000010010001001001101101011", "00000000010010001010100000000100", "00000000010010001011110010101001", "00000000010010001101000101011001", "00000000010010001110011000010110", "00000000010010001111101011011110", "00000000010010010000111110110010", "00000000010010010010010010010010", "00000000010010010011100101111110", "00000000010010010100111001110101", "00000000010010010110001101111001", "00000000010010010111100010001001", "00000000010010011000110110100101", "00000000010010011010001011001101", "00000000010010011011100000000010", "00000000010010011100110101000010", "00000000010010011110001010001111", "00000000010010011111011111101000", "00000000010010100000110101001110", "00000000010010100010001011000000", "00000000010010100011100000111110", "00000000010010100100110111001001", "00000000010010100110001101100000", "00000000010010100111100100000100", "00000000010010101000111010110101", "00000000010010101010010001110010", "00000000010010101011101000111100", "00000000010010101101000000010010", "00000000010010101110010111110110", "00000000010010101111101111100110", "00000000010010110001000111100011", "00000000010010110010011111101101", "00000000010010110011111000000100", "00000000010010110101010000101000", "00000000010010110110101001011000", "00000000010010111000000010010111", "00000000010010111001011011100010", "00000000010010111010110100111010", "00000000010010111100001110100000", "00000000010010111101101000010010", "00000000010010111111000010010011", "00000000010011000000011100100000", "00000000010011000001110110111011", "00000000010011000011010001100100", "00000000010011000100101100011001", "00000000010011000110000111011101", "00000000010011000111100010101110", "00000000010011001000111110001101", "00000000010011001010011001111001", "00000000010011001011110101110011", "00000000010011001101010001111011", "00000000010011001110101110010001", "00000000010011010000001010110101", "00000000010011010001100111100110", "00000000010011010011000100100110", "00000000010011010100100001110011", "00000000010011010101111111001111", "00000000010011010111011100111001", "00000000010011011000111010110001", "00000000010011011010011000110111", "00000000010011011011110111001100", "00000000010011011101010101101111", "00000000010011011110110100100000", "00000000010011100000010011100000", "00000000010011100001110010101110", "00000000010011100011010010001011", "00000000010011100100110001110110", "00000000010011100110010001110000", "00000000010011100111110001111001", "00000000010011101001010010010000", "00000000010011101010110010110111", "00000000010011101100010011101100", "00000000010011101101110100110000", "00000000010011101111010110000011", "00000000010011110000110111100101", "00000000010011110010011001010110", "00000000010011110011111011010110", "00000000010011110101011101100110", "00000000010011110111000000000100", "00000000010011111000100010110010", "00000000010011111010000101110000", "00000000010011111011101000111101", "00000000010011111101001100011001", "00000000010011111110110000000100", "00000000010100000000010100000000", "00000000010100000001111000001011", "00000000010100000011011100100101", "00000000010100000101000001010000", "00000000010100000110100110001010", "00000000010100001000001011010100", "00000000010100001001110000101110", "00000000010100001011010110011000", "00000000010100001100111100010010", "00000000010100001110100010011100", "00000000010100010000001000110111", "00000000010100010001101111100001", "00000000010100010011010110011100", "00000000010100010100111101100111", "00000000010100010110100101000011", "00000000010100011000001100101111", "00000000010100011001110100101011", "00000000010100011011011100111000", "00000000010100011101000101010110", "00000000010100011110101110000101", "00000000010100100000010111000100", "00000000010100100010000000010100", "00000000010100100011101001110101", "00000000010100100101010011100111", "00000000010100100110111101101010", "00000000010100101000100111111110", "00000000010100101010010010100011", "00000000010100101011111101011010", "00000000010100101101101000100010", "00000000010100101111010011111011", "00000000010100110000111111100110", "00000000010100110010101011100010", "00000000010100110100010111101111", "00000000010100110110000100001110", "00000000010100110111110000111111", "00000000010100111001011110000010", "00000000010100111011001011010111", "00000000010100111100111000111101", "00000000010100111110100110110101", "00000000010101000000010101000000", "00000000010101000010000011011100", "00000000010101000011110010001011", "00000000010101000101100001001100", "00000000010101000111010000011111", "00000000010101001001000000000101", "00000000010101001010101111111101", "00000000010101001100100000000111", "00000000010101001110010000100101", "00000000010101010000000001010101", "00000000010101010001110010010111", "00000000010101010011100011101101", "00000000010101010101010101010101", "00000000010101010111000111010000", "00000000010101011000111001011110", "00000000010101011010101100000000", "00000000010101011100011110110100", "00000000010101011110010001111100", "00000000010101100000000101011000", "00000000010101100001111001000110", "00000000010101100011101101001000", "00000000010101100101100001011110", "00000000010101100111010110000111", "00000000010101101001001011000100", "00000000010101101011000000010101", "00000000010101101100110101111010", "00000000010101101110101011110011", "00000000010101110000100001111111", "00000000010101110010011000100000", "00000000010101110100001111010101", "00000000010101110110000110011111", "00000000010101110111111101111100", "00000000010101111001110101101110", "00000000010101111011101101110101", "00000000010101111101100110010000", "00000000010101111111011111000000", "00000000010110000001011000000101", "00000000010110000011010001011111", "00000000010110000101001011001101", "00000000010110000111000101010001", "00000000010110001000111111101001", "00000000010110001010111010010111", "00000000010110001100110101011010", "00000000010110001110110000110011", "00000000010110010000101100100001", "00000000010110010010101000100100", "00000000010110010100100100111110", "00000000010110010110100001101100", "00000000010110011000011110110001", "00000000010110011010011100001100", "00000000010110011100011001111100", "00000000010110011110011000000011", "00000000010110100000010110100000", "00000000010110100010010101010011", "00000000010110100100010100011100", "00000000010110100110010011111100", "00000000010110101000010011110011", "00000000010110101010010100000000", "00000000010110101100010100100100", "00000000010110101110010101011110", "00000000010110110000010110110000", "00000000010110110010011000011000", "00000000010110110100011010011000", "00000000010110110110011100101111", "00000000010110111000011111011101", "00000000010110111010100010100011", "00000000010110111100100110000000", "00000000010110111110101001110101", "00000000010111000000101110000001", "00000000010111000010110010100101", "00000000010111000100110111100001", "00000000010111000110111100110101", "00000000010111001001000010100001", "00000000010111001011001000100110", "00000000010111001101001111000011", "00000000010111001111010101111000", "00000000010111010001011101000101", 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process(DENOMINATOR,RESET) begin if RESET = '1' then DENOMINATOR2 <= "0000000010"; else DENOMINATOR2 <= DENOMINATOR; end if; end process INIT; SETNUMERATOR : process (CLOCK) begin if CLOCK'event and CLOCK = '1' then if RESET = '1' then NUMERATOR2 <= "0000000001"; else NUMERATOR2 <= NUMERATOR; end if; end if; end process SETNUMERATOR; INDEX <= DENOMINATOR2 - "0000000010"; LOOKUP: process(CLOCK) begin if CLOCK'event and CLOCK = '1' then RECIPROCAL <= LUT(conv_integer(INDEX)); end if; end process LOOKUP; DIVIDE1: process(CLOCK) begin if CLOCK'event and CLOCK='1' then PRODUCT1<=NUMERATOR2*RECIPROCAL(31 downto 16); end if; end process DIVIDE1; DIVIDE2: process(CLOCK) begin if CLOCK'event and CLOCK='1' then PRODUCT2<=NUMERATOR2*RECIPROCAL(15 downto 0); end if; end process DIVIDE2; TOTAL<=((PRODUCT1 & "0000000000000000") + ("0000000000000000" & PRODUCT2)); QUOTIENT <= TOTAL(31 downto 22); end RTL; 1.1 dirac/src/common/HALVING_MANAGER.vhd http://www.opencores.org/cvsweb.shtml/dirac/src/common/HALVING_MANAGER.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: HALVING_MANAGER.vhd =================================================================== -- ***** BEGIN LICENSE BLOCK ***** -- -- -- Version: MPL 1.1/GPL 2.0/LGPL 2.1 -- -- The contents of this file are subject to the Mozilla Public License -- Version 1.1 (the "License"); you may not use this file except in compliance -- with the License. You may obtain a copy of the License at -- http://www.mozilla.org/MPL/ -- -- Software distributed under the License is distributed on an "AS IS" basis, -- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for -- the specific language governing rights and limitations under the License. -- -- The Original Code is BBC Research and Development code. -- -- The Initial Developer of the Original Code is the British Broadcasting -- Corporation. -- Portions created by the Initial Developer are Copyright (C) 2006. -- All Rights Reserved. -- -- Contributor(s): Peter Bleackley (Original author) -- -- Alternatively, the contents of this file may be used under the terms of -- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser -- Public License Version 2.1 (the "LGPL"), in which case the provisions of -- the GPL or the LGPL are applicable instead of those above. If you wish to -- allow use of your version of this file only under the terms of the either -- the GPL or LGPL and not to allow others to use your version of this file -- under the MPL, indicate your decision by deleting the provisions above -- and replace them with the notice and other provisions required by the GPL -- or LGPL. If you do not delete the provisions above, a recipient may use -- your version of this file under the terms of any one of the MPL, the GPL -- or the LGPL. -- * ***** END LICENSE BLOCK ***** */ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity HALVING_MANAGER is Port ( TRIGGER_HALVING : in std_logic; INPUT_READY : in std_logic; NUMERATOR_IN : in std_logic_vector(9 downto 0); DENOMINATOR_IN : in std_logic_vector(9 downto 0); CONTEXT : in std_logic_vector(5 downto 0); RESET : in std_logic; CLOCK : in std_logic; NUMERATOR_OUT : out std_logic_vector(9 downto 0); DENOMINATOR_OUT : out std_logic_vector(9 downto 0); OUTPUT_READY : out std_logic); end HALVING_MANAGER; architecture RTL of HALVING_MANAGER is type COUNTARRAY is array(45 downto 0) of std_logic_vector(2 downto 0); signal SHIFTS : COUNTARRAY; signal NUMERATOR : std_logic_vector (9 downto 0); signal DENOMINATOR : std_logic_vector (9 downto 0); signal NUMERATOR2 : std_logic_vector (9 downto 0); signal DENOMINATOR2 : std_logic_vector (9 downto 0); signal DENOMINATOR_INCREMENT : std_logic_vector (9 downto 0); signal GREATER_THAN_16 : std_logic; signal PERFORM_HALVING : std_logic; signal AFTER_TRIGGER : std_logic; signal LOAD : std_logic; signal CALCULATE_VALUES : std_logic; begin COUNT_HALVING_EVENTS : process (CLOCK) begin if CLOCK'event and CLOCK = '1' then if RESET = '1' then SHIFTS <= (others => "000"); elsif TRIGGER_HALVING = '1' then for I in 0 to 45 loop if SHIFTS(I) /= "111" then SHIFTS(I) <= SHIFTS(I) + "001"; end if; end loop; elsif CALCULATE_VALUES = '1' then SHIFTS(conv_integer(CONTEXT)) <= SHIFTS(conv_integer(CONTEXT)) - "001"; elsif GREATER_THAN_16 = '0' and LOAD = '0' and INPUT_READY = '1' then SHIFTS(conv_integer(CONTEXT)) <= "000"; end if; end if; end process COUNT_HALVING_EVENTS; NUMERATOR2 <= ('0' & NUMERATOR (9 downto 1)) + "0000000001"; DENOMINATOR2 <= ('0' & DENOMINATOR(9 downto 1)) + DENOMINATOR_INCREMENT; HALVE_COUNTS : process (CLOCK) begin if CLOCK'event and CLOCK='1' then if RESET = '1' then NUMERATOR <= "0000000001"; DENOMINATOR <= "0000000010"; elsif CALCULATE_VALUES = '1' then NUMERATOR <= NUMERATOR2; DENOMINATOR <= DENOMINATOR2; elsif LOAD = '1' then NUMERATOR <= NUMERATOR_IN; DENOMINATOR <= DENOMINATOR_IN; end if; end if; end process HALVE_COUNTS; HALVING_PERMITTED : process (DENOMINATOR) begin if DENOMINATOR > "0000010000" then GREATER_THAN_16 <= '1'; else GREATER_THAN_16 <= '0'; end if; end process HALVING_PERMITTED; HALVING_ACTIVE : process (INPUT_READY, SHIFTS, CONTEXT, GREATER_THAN_16) begin if INPUT_READY = '1' and (SHIFTS(conv_integer(CONTEXT)) > "000") then PERFORM_HALVING <= GREATER_THAN_16; else PERFORM_HALVING <= '0'; end if; end process HALVING_ACTIVE; SELECT_OUTPUT : process (NUMERATOR_IN, DENOMINATOR_IN, NUMERATOR, DENOMINATOR, TRIGGER_HALVING, PERFORM_HALVING, LOAD) begin if (LOAD and (TRIGGER_HALVING nor PERFORM_HALVING)) = '1' then NUMERATOR_OUT <= NUMERATOR_IN; DENOMINATOR_OUT <= DENOMINATOR_IN; else NUMERATOR_OUT <= NUMERATOR; DENOMINATOR_OUT <= DENOMINATOR; end if; end process SELECT_OUTPUT; DELAY_TRIGGER : process (CLOCK) begin if CLOCK'event and CLOCK = '1' then if RESET = '1' then AFTER_TRIGGER <= '0'; else AFTER_TRIGGER <= INPUT_READY; end if; end if; end process DELAY_TRIGGER; CHOOSE_DENOMINATOR_INCREMENT : process (NUMERATOR, DENOMINATOR) begin if (NUMERATOR (0) = '1') and (DENOMINATOR (0) = '0') then DENOMINATOR_INCREMENT <= "0000000001"; else DENOMINATOR_INCREMENT <= "0000000010"; end if; end process CHOOSE_DENOMINATOR_INCREMENT; LOAD <= INPUT_READY and not AFTER_TRIGGER; CALCULATE_VALUES <= PERFORM_HALVING and AFTER_TRIGGER; OUTPUT_READY <= INPUT_READY and (PERFORM_HALVING nor TRIGGER_HALVING); end RTL; 1.1 dirac/src/common/UPDATER.vhd http://www.opencores.org/cvsweb.shtml/dirac/src/common/UPDATER.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: UPDATER.vhd =================================================================== -- ***** BEGIN LICENSE BLOCK ***** -- -- -- Version: MPL 1.1/GPL 2.0/LGPL 2.1 -- -- The contents of this file are subject to the Mozilla Public License -- Version 1.1 (the "License"); you may not use this file except in compliance -- with the License. You may obtain a copy of the License at -- http://www.mozilla.org/MPL/ -- -- Software distributed under the License is distributed on an "AS IS" basis, -- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for -- the specific language governing rights and limitations under the License. -- -- The Original Code is BBC Research and Development code. -- -- The Initial Developer of the Original Code is the British Broadcasting -- Corporation. -- Portions created by the Initial Developer are Copyright (C) 2006. -- All Rights Reserved. -- -- Contributor(s): Peter Bleackley (Original author) -- -- Alternatively, the contents of this file may be used under the terms of -- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser -- Public License Version 2.1 (the "LGPL"), in which case the provisions of -- the GPL or the LGPL are applicable instead of those above. If you wish to -- allow use of your version of this file only under the terms of the either -- the GPL or LGPL and not to allow others to use your version of this file -- under the MPL, indicate your decision by deleting the provisions above -- and replace them with the notice and other provisions required by the GPL -- or LGPL. If you do not delete the provisions above, a recipient may use -- your version of this file under the terms of any one of the MPL, the GPL -- or the LGPL. -- * ***** END LICENSE BLOCK ***** */ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity UPDATER is Port ( NUMERATOR : in std_logic_vector(9 downto 0); DENOMINATOR : in std_logic_vector(9 downto 0); ENABLE : in std_logic; DATA_IN : in std_logic; RESET : in std_logic; CLOCK : in std_logic; NUMERATOR_OUT : out std_logic_vector(9 downto 0); DENOMINATOR_OUT : out std_logic_vector(9 downto 0); UPDATE : out std_logic); end UPDATER; architecture RTL of UPDATER is signal NUMERATOR1 : std_logic_vector(9 downto 0); signal NUMERATOR2 : std_logic_vector(9 downto 0); signal NUMERATOR3 : std_logic_vector(9 downto 0); signal NUMERATOR4 : std_logic_vector(9 downto 0); signal DENOMINATOR2 : std_logic_vector(9 downto 0); signal HALVE_VALUES : std_logic; signal HALVING_ALLOWED : std_logic; signal UPDATE_SWITCH : std_logic; begin DELAY_NUMERATOR : process (CLOCK) begin if CLOCK'event and CLOCK='1' then if RESET='1' then NUMERATOR1<="0000000001"; else NUMERATOR1<=NUMERATOR; end if; end if; end process DELAY_NUMERATOR; INCREMENT_NUMERATOR : process (CLOCK) begin if CLOCK'event and CLOCK = '1' then if RESET = '1' then NUMERATOR2 <= "0000000001"; else NUMERATOR2 <= NUMERATOR + "0000000001"; end if; end if; end process INCREMENT_NUMERATOR; HALVE_NUMERATOR : process (CLOCK) begin if CLOCK'event and CLOCK='1' then if RESET='1' then NUMERATOR3 <= "0000000001"; else NUMERATOR3 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001"; end if; end if; end process HALVE_NUMERATOR; INCREMENT_AND_HALVE_NUMERATOR : process (CLOCK) begin if CLOCK'event and CLOCK='1' then if RESET='1' then NUMERATOR4 <= "0000000001"; else NUMERATOR4 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001" + ("000000000" & NUMERATOR(0)); end if; end if; end process INCREMENT_AND_HALVE_NUMERATOR; INCREMENT_DENOMINATOR : process (CLOCK) begin if CLOCK'event and CLOCK='1' then if RESET='1' then DENOMINATOR2 <= "0000000010"; else DENOMINATOR2 <= DENOMINATOR + "0000000001"; end if; end if; end process INCREMENT_DENOMINATOR; HALVE_DENOMINATOR : process (DENOMINATOR) begin if (DENOMINATOR = "1111111111") then HALVE_VALUES <= '1'; else HALVE_VALUES <= '0'; end if; end process HALVE_DENOMINATOR; OUTPUT_NUMERATOR : process(NUMERATOR1,NUMERATOR2,NUMERATOR3,NUMERATOR4,DENOMINATOR,DATA_IN,HALVE_VALUES) begin if HALVE_VALUES='1' then if DATA_IN='1' then NUMERATOR_OUT <= NUMERATOR3; else NUMERATOR_OUT <= NUMERATOR4; end if; else if DATA_IN='1' then NUMERATOR_OUT <= NUMERATOR1; else NUMERATOR_OUT <= NUMERATOR2; end if; end if; end process OUTPUT_NUMERATOR; UPDATE_SWITCH <= DATA_IN xor NUMERATOR(0); OUTPUT_DENOMINATOR : process(HALVING_ALLOWED,DENOMINATOR,DENOMINATOR2,UPDATE_SWITCH,HALVE_VALUES,NUMERATOR) begin if HALVE_VALUES='1' then if UPDATE_SWITCH = '1' then DENOMINATOR_OUT <= "1000000010"; else DENOMINATOR_OUT <= "1000000001"; end if; else DENOMINATOR_OUT<=DENOMINATOR2; end if; end process OUTPUT_DENOMINATOR; OUTPUT_READY : process (CLOCK) begin if CLOCK'event and CLOCK='1' then if RESET='1' then UPDATE <= '0'; else UPDATE <= ENABLE; end if; end if; end process OUTPUT_READY; end RTL;

     
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