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Message
From: cvs at opencores.org<cvs@o...>
Date: Thu Aug 17 13:18:35 CEST 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/08 17:13:18 Modified: jop/vhdl/memory sc_sram16.vhd
Log:
nwr goes low befor ncs to allow single cycle SRAM
Revision Changes Path
1.7 jop/vhdl/memory/sc_sram16.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/memory/sc_sram16.vhd.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: sc_sram16.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/memory/sc_sram16.vhd,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- sc_sram16.vhd 17 Aug 2006 11:05:23 -0000 1.6
+++ sc_sram16.vhd 17 Aug 2006 11:18:35 -0000 1.7
@@ -96,7 +96,6 @@
ram_addr <= (others => '0');
ram_dout <= (others => '0');
--- rd_data <= (others => '0');
ram_dout_low <= (others => '0');
elsif rising_edge(clk) then
@@ -116,14 +115,12 @@
end if;
if rd_data_ena_h='1' then
ram_din_reg(15 downto 0) <= ram_din;
--- rd_data(31 downto 16) <= ram_din;
end if;
if rd_data_ena_l='1' then
-- move first word to higher half
ram_din_reg(31 downto 16) <= ram_din_reg(15 downto 0);
-- read second word
ram_din_reg(15 downto 0) <= ram_din;
--- rd_data(15 downto 0) <= ram_din;
end if;
end if;
@@ -314,8 +311,14 @@
begin
nwr_int <= '1';
- if (state=wr_l and next_state=wr_l) or
- (state=wr_h and next_state=wr_h) then
+ -- this is the 'correct' version wich needs
+ -- at minimum 2 cycles for the RAM access
+-- if (state=wr_l and next_state=wr_l) or
+-- (state=wr_h and next_state=wr_h) then
+ -- Slightly out of the SRAM spec. nwr goes
+ -- low befor ncs to allow single cycle
+ -- access
+ if next_state=wr_l or next_state=wr_h then
nwr_int <= '0';
end if;
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