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Message
From: cvs at opencores.org<cvs@o...>
Date: Thu Aug 17 13:05:23 CEST 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/08 17:13:05 Modified: jop/vhdl/memory sc_sram16.vhd
Log:
pipelined read, works with single wait state. 0 wait state does not
generate a write signal
Revision Changes Path
1.6 jop/vhdl/memory/sc_sram16.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/memory/sc_sram16.vhd.diff?r1=1.5&r2=1.6
(In the diff below, changes in quantity of whitespace are not shown.)
Index: sc_sram16.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/memory/sc_sram16.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- sc_sram16.vhd 17 Aug 2006 00:30:37 -0000 1.5
+++ sc_sram16.vhd 17 Aug 2006 11:05:23 -0000 1.6
@@ -195,16 +195,16 @@
next_state <= idl;
-- This should do to give us a pipeline
-- level of 2 for read
--- if rd='1' then
--- if ram_ws=0 then
--- -- then we omit state rd1!
--- next_state <= rd2_h;
--- else
--- next_state <= rd1_h;
--- end if;
--- elsif wr='1' then
--- next_state <= wr_h;
--- end if;
+ if rd='1' then
+ if ram_ws=0 then
+ -- then we omit state rd1!
+ next_state <= rd2_h;
+ else
+ next_state <= rd1_h;
+ end if;
+ elsif wr='1' then
+ next_state <= wr_h;
+ end if;
-- the WS state
when wr_h =>
@@ -345,19 +345,24 @@
if state=rd2_h or state=wr_idl then
wait_state <= to_unsigned(ram_ws+1, 4);
--- if ram_ws<3 then
--- cnt <= to_unsigned(ram_ws+1, 2);
--- else
--- cnt <= "11";
--- end if;
+ if ram_ws<3 then
+ cnt <= to_unsigned(ram_ws+1, 2);
+ else
+ cnt <= "11";
+ end if;
end if;
if state=rd1_l or state=rd2_l or state=wr_l then
+ -- take care for pipelined cach transfer
+ -- there is no idl state and cnt should
+ -- go back to "11"
+ if rd='0' and wr='0' then
-- if wait_state<4 then
if wait_state(3 downto 2)="00" then
cnt <= wait_state(1 downto 0)-1;
end if;
end if;
+ end if;
end if;
end process;
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