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Message
From: cvs at opencores.org<cvs@o...>
Date: Thu Aug 17 02:16:34 CEST 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/08 17:02:16 Modified: jop/vhdl/memory sc_sram16.vhd
Log:
din register without a MUX
Revision Changes Path
1.4 jop/vhdl/memory/sc_sram16.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/memory/sc_sram16.vhd.diff?r1=1.3&r2=1.4
(In the diff below, changes in quantity of whitespace are not shown.)
Index: sc_sram16.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/memory/sc_sram16.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- sc_sram16.vhd 17 Aug 2006 00:09:21 -0000 1.3
+++ sc_sram16.vhd 17 Aug 2006 00:16:34 -0000 1.4
@@ -94,7 +94,7 @@
ram_addr <= (others => '0');
ram_dout <= (others => '0');
- rd_data <= (others => '0');
+-- rd_data <= (others => '0');
ram_dout_low <= (others => '0');
elsif rising_edge(clk) then
@@ -113,21 +113,21 @@
ram_dout <= ram_dout_low;
end if;
if rd_data_ena_h='1' then
--- ram_din_reg(15 downto 0) <= ram_din;
- rd_data(31 downto 16) <= ram_din;
+ ram_din_reg(15 downto 0) <= ram_din;
+-- rd_data(31 downto 16) <= ram_din;
end if;
if rd_data_ena_l='1' then
--- -- move first word to higher half
--- ram_din_reg(31 downto 16) <= ram_din_reg(15 downto 0);
--- -- read second word
--- ram_din_reg(15 downto 0) <= ram_din;
- rd_data(15 downto 0) <= ram_din;
+ -- move first word to higher half
+ ram_din_reg(31 downto 16) <= ram_din_reg(15 downto 0);
+ -- read second word
+ ram_din_reg(15 downto 0) <= ram_din;
+-- rd_data(15 downto 0) <= ram_din;
end if;
end if;
end process;
--- rd_data <= ram_din_reg;
+ rd_data <= ram_din_reg;
--
-- 'delay' nwe 1/2 cycle -> change on falling edge
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