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From: cvs at opencores.org<cvs@o...>
Date: Tue Aug 15 20:03:12 CEST 2006
Subject: [cvs-checkins] MODIFIED: matrix3x3 ...
Date: 00/06/08 15:20:03

Modified: matrix3x3/rtl/vhdl colorconv.vhd
Log:
was error in shift register


Revision Changes Path
1.2 matrix3x3/rtl/vhdl/colorconv.vhd

http://www.opencores.org/cvsweb.shtml/matrix3x3/rtl/vhdl/colorconv.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: colorconv.vhd
===================================================================
RCS file: /cvsroot/vv_gulyaev/matrix3x3/rtl/vhdl/colorconv.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- colorconv.vhd 14 Aug 2006 22:55:02 -0000 1.1
+++ colorconv.vhd 15 Aug 2006 18:03:12 -0000 1.2
@@ -62,7 +62,7 @@

signal y1w,y2w,y3w : SIGNED( (data_width+factors_width) downto 0 );

-signal pipe_delay : STD_LOGIC_VECTOR( 10 downto 0 );
+signal pipe_delay : STD_LOGIC_VECTOR( 7 downto 0 );

begin

@@ -181,11 +181,11 @@
pipe_delay <= (others=>'0');
elsif rising_edge(clk) then
pipe_delay(0) <= DATA_ENA;
- pipe_delay(8 downto 1) <= pipe_delay(7 downto 0);
+ pipe_delay(7 downto 1) <= pipe_delay(6 downto 0);
end if;
end process;

-DOUT_RDY <= pipe_delay(8);
+DOUT_RDY <= pipe_delay(7);


end a;