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From: cvs at opencores.org<cvs@o...>
Date: Mon Aug 14 00:39:05 CEST 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/08 14:00:39

Modified: jop/sopc/components/sram_256k_x_32bit class.ptf
Log:
timing in ns


Revision Changes Path
1.2 jop/sopc/components/sram_256k_x_32bit/class.ptf

http://www.opencores.org/cvsweb.shtml/jop/sopc/components/sram_256k_x_32bit/class.ptf.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: class.ptf
===================================================================
RCS file: /cvsroot/martin/jop/sopc/components/sram_256k_x_32bit/class.ptf,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- class.ptf 13 Aug 2006 20:07:37 -0000 1.1
+++ class.ptf 13 Aug 2006 22:39:05 -0000 1.2
@@ -1,6 +1,6 @@
#
# This class.ptf file built by Component Editor
-# 2006.08.13.18:34:04
+# 2006.08.13.21:33:06
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
@@ -100,10 +100,10 @@
Data_Width = "32";
Has_Base_Address = "1";
Has_IRQ = "0";
- Setup_Time = "0cycles";
- Hold_Time = "0cycles";
- Read_Wait_States = "1cycles";
- Write_Wait_States = "1cycles";
+ Setup_Time = "0ns";
+ Hold_Time = "2ns";
+ Read_Wait_States = "18ns";
+ Write_Wait_States = "10ns";
Read_Latency = "0";
Maximum_Pending_Read_Transactions = "0";
Active_CS_Through_Read_Latency = "0";
@@ -118,10 +118,10 @@
ATS_SETTINGS
{
Setup_Value = "0";
- Read_Wait_Value = "1";
- Write_Wait_Value = "1";
- Hold_Value = "0";
- Timing_Units = "cycles";
+ Read_Wait_Value = "18";
+ Write_Wait_Value = "10";
+ Hold_Value = "2";
+ Timing_Units = "ns";
Read_Latency_Value = "0";
Minimum_Arbitration_Shares = "1";
Active_CS_Through_Read_Latency = "0";
@@ -225,7 +225,7 @@
layout = "vertical";
TEXT
{
- title = "Built on: 2006.08.13.18:34:04";
+ title = "Built on: 2006.08.13.21:33:06";
}
TEXT
{
@@ -258,7 +258,7 @@
SW_FILES
{
}
- built_on = "2006.08.13.18:34:04";
+ built_on = "2006.08.13.21:33:06";
CACHED_HDL_INFO
{
# cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection