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From: cvs at opencores.org<cvs@o...>
Date: Mon Aug 14 00:19:32 CEST 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/08 14:00:19

Modified: jop/vhdl/scio sc_uart.vhd sc_uart_tal.vhd
Log:
3 FFs on exd input pin to help Quartus for tsu


Revision Changes Path
1.4 jop/vhdl/scio/sc_uart.vhd

http://www.opencores.org/cvsweb.shtml/jop/vhdl/scio/sc_uart.vhd.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: sc_uart.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/scio/sc_uart.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- sc_uart.vhd 10 Aug 2006 22:28:39 -0000 1.3
+++ sc_uart.vhd 13 Aug 2006 22:19:31 -0000 1.4
@@ -32,6 +32,7 @@
-- 2004-03-23 two stop bits
-- 2005-11-30 change interface to SimpCon
-- 2006-08-07 rxd input register with clk to avoid Quartus tsu violation
+-- 2006-08-13 use 3 FFs for the rxd input at clk
--


@@ -117,7 +118,7 @@
signal rf_full : std_logic;
signal rf_half : std_logic;

- signal rxd_reg : std_logic;
+ signal rxd_reg : std_logic_vector(2 downto 0);
signal rx_buf : std_logic_vector(2 downto 0); -- sync in, filter
signal rx_d : std_logic; -- rx serial data

@@ -181,7 +182,9 @@

elsif rising_edge(clk) then

- rxd_reg <= rxd; -- to avoid setup timing error in Quartus
+ rxd_reg(0) <= rxd; -- to avoid setup timing error in Quartus
+ rxd_reg(1) <= rxd_reg(0);
+ rxd_reg(2) <= rxd_reg(1);

if (clk16=clk16_cnt) then -- 16 x serial clock
clk16 := 0;
@@ -210,7 +213,7 @@
--
-- sync in filter buffer
--
- rx_buf(0) <= rxd_reg;
+ rx_buf(0) <= rxd_reg(2);
rx_buf(2 downto 1) <= rx_buf(1 downto 0);
else
clk16 := clk16 + 1;



1.2 jop/vhdl/scio/sc_uart_tal.vhd

http://www.opencores.org/cvsweb.shtml/jop/vhdl/scio/sc_uart_tal.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: sc_uart_tal.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/scio/sc_uart_tal.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- sc_uart_tal.vhd 29 Dec 2005 10:56:46 -0000 1.1
+++ sc_uart_tal.vhd 13 Aug 2006 22:19:31 -0000 1.2
@@ -36,6 +36,7 @@
-- 2004-04-26 DTR is inverted conf_reg(0) => '1' means set DTR!
-- 2005-02-28 Changed default conf_reg to no hand shake (ignore ncts)
-- 2005-12-27 change interface to SimpCon
+-- 2006-08-13 use 3 FFs for the rxd input at clk
--


@@ -125,7 +126,7 @@
signal rf_full : std_logic;
signal rf_half : std_logic;

- signal rxd_reg : std_logic;
+ signal rxd_reg : std_logic_vector(2 downto 0);
signal rx_buf : std_logic_vector(2 downto 0); -- sync in, filter
signal rx_d : std_logic; -- rx serial data

@@ -217,6 +218,10 @@

elsif rising_edge(clk) then

+ rxd_reg(0) <= rxd; -- to avoid setup timing error in Quartus
+ rxd_reg(1) <= rxd_reg(0);
+ rxd_reg(2) <= rxd_reg(1);
+
if (clk16=clk16_cnt) then -- 16 x serial clock
clk16 := 0; -- @@ -244,8 +249,7 @@ -- -- sync in filter buffer -- - rxd_reg <= rxd; -- to avoid setup timing error in Quartus - rx_buf(0) <= rxd_reg; + rx_buf(0) <= rxd_reg(2); rx_buf(2 downto 1) <= rx_buf(1 downto 0); else clk16 := clk16 + 1;