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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Aug 12 02:45:06 CEST 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/08 12:02:45 Modified: jop/quartus/altde2 jop_system.ptf
Log:
SDRAM added
Revision Changes Path
1.4 jop/quartus/altde2/jop_system.ptf
http://www.opencores.org/cvsweb.shtml/jop/quartus/altde2/jop_system.ptf.diff?r1=1.3&r2=1.4
(In the diff below, changes in quantity of whitespace are not shown.)
Index: jop_system.ptf
===================================================================
RCS file: /cvsroot/martin/jop/quartus/altde2/jop_system.ptf,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- jop_system.ptf 11 Aug 2006 19:32:10 -0000 1.3
+++ jop_system.ptf 12 Aug 2006 00:45:06 -0000 1.4
@@ -396,7 +396,7 @@
{
priority = "1";
}
- Base_Address = "0x00000000";
+ Base_Address = "0x01000000";
}
COMPONENT_BUILDER
{
@@ -484,4 +484,628 @@
}
}
}
+ MODULE onchip_memory_0
+ {
+ class = "altera_avalon_onchip_memory2";
+ class_version = "6.01";
+ iss_model_name = "altera_memory";
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory_0.vhd";
+ Synthesis_Only_Files = "";
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ allow_mram_sim_contents_only_file = "0";
+ ram_block_type = "M4K";
+ init_contents_file = "onchip_memory_0";
+ non_default_init_file_enabled = "0";
+ gui_ram_block_type = "Automatic";
+ Writeable = "1";
+ dual_port = "0";
+ Size_Value = "32";
+ Size_Multiple = "1024";
+ MAKE
+ {
+ TARGET delete_placeholder_warning
+ {
+ onchip_memory_0
+ {
+ Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
+ Is_Phony = "1";
+ Target_File = "do_delete_placeholder_warning";
+ }
+ }
+ TARGET hex
+ {
+ onchip_memory_0
+ {
+ Command1 = "@echo Post-processing to create $(notdir $@)";
+ Command2 = "elf2hex $(ELF) 0x00000000 0x9FFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory_0.hex --create-lanes=0 ";
+ Dependency = "$(ELF)";
+ Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory_0.hex";
+ }
+ }
+ TARGET sim
+ {
+ onchip_memory_0
+ {
+ Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
+ Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
+ Command3 = "touch $(SIMDIR)/dummy_file";
+ Dependency = "$(ELF)";
+ Target_File = "$(SIMDIR)/dummy_file";
+ }
+ }
+ }
+ contents_info = "QUARTUS_PROJECT_DIR/onchip_memory_0.hex 1155328240 ";
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
+ Instantiate_In_System_Module = "1";
+ Is_Enabled = "0";
+ Default_Module_Name = "onchip_memory";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Is_Collapsed = "1";
+ }
+ }
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT address
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "address";
+ width = "14";
+ }
+ PORT byteenable
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "byteenable";
+ width = "4";
+ }
+ PORT chipselect
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "chipselect";
+ width = "1";
+ }
+ PORT clk
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "clk";
+ width = "1";
+ }
+ PORT clken
+ {
+ Is_Enabled = "1";
+ default_value = "1'b1";
+ direction = "input";
+ type = "clken";
+ width = "1";
+ }
+ PORT readdata
+ {
+ Is_Enabled = "1";
+ direction = "output";
+ type = "readdata";
+ width = "32";
+ }
+ PORT write
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "write";
+ width = "1";
+ }
+ PORT writedata
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "writedata";
+ width = "32";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Is_Memory_Device = "1";
+ Address_Group = "0";
+ Address_Alignment = "dynamic";
+ Address_Width = "13";
+ Data_Width = "32";
+ Has_IRQ = "0";
+ Read_Wait_States = "0";
+ Write_Wait_States = "0";
+ Address_Span = "32768";
+ Read_Latency = "1";
+ Is_Channel = "1";
+ Is_Writable = "1";
+ MASTERED_BY jop_avalon_0/avalon_master
+ {
+ priority = "1";
+ }
+ Base_Address = "0x00000000";
+ }
+ }
+ SLAVE s2
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Is_Memory_Device = "1";
+ Address_Group = "0";
+ Address_Alignment = "dynamic";
+ Address_Width = "13";
+ Data_Width = "32";
+ Has_IRQ = "0";
+ Read_Wait_States = "0";
+ Write_Wait_States = "0";
+ Address_Span = "32768";
+ Read_Latency = "1";
+ Is_Channel = "1";
+ Is_Enabled = "0";
+ Is_Writable = "1";
+ }
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = "chipselect";
+ conditional = "1";
+ }
+ SIGNAL b
+ {
+ name = "write";
+ conditional = "1";
+ }
+ SIGNAL c
+ {
+ name = "address";
+ radix = "hexadecimal";
+ }
+ SIGNAL d
+ {
+ name = "byteenable";
+ radix = "binary";
+ conditional = "1";
+ }
+ SIGNAL e
+ {
+ name = "readdata";
+ radix = "hexadecimal";
+ }
+ SIGNAL f
+ {
+ name = "writedata";
+ radix = "hexadecimal";
+ conditional = "1";
+ }
+ }
+ }
+ PORT_WIRING
+ {
+ }
+ }
+ MODULE sdram
+ {
+ class = "altera_avalon_new_sdram_controller";
+ class_version = "6.01";
+ iss_model_name = "altera_memory";
+ SLAVE s1
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Address_Alignment = "dynamic";
+ Has_IRQ = "0";
+ Maximum_Pending_Read_Transactions = "7";
+ Read_Wait_States = "peripheral_controlled";
+ Write_Wait_States = "peripheral_controlled";
+ Is_Memory_Device = "1";
+ Address_Width = "22";
+ Data_Width = "16";
+ Simulation_Num_Lanes = "1";
+ MASTERED_BY jop_avalon_0/avalon_master
+ {
+ priority = "1";
+ }
+ Base_Address = "0x00000000";
+ Address_Group = "0";
+ }
+ PORT_WIRING
+ {
+ PORT zs_addr
+ {
+ direction = "output";
+ width = "12";
+ Is_Enabled = "1";
+ }
+ PORT zs_ba
+ {
+ direction = "output";
+ width = "2";
+ Is_Enabled = "1";
+ }
+ PORT zs_cas_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ PORT zs_cke
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ PORT zs_cs_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ PORT zs_dq
+ {
+ direction = "inout";
+ width = "16";
+ Is_Enabled = "1";
+ }
+ PORT zs_dqm
+ {
+ direction = "output";
+ width = "2";
+ Is_Enabled = "1";
+ }
+ PORT zs_ras_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ PORT zs_we_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ PORT az_addr
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "address";
+ width = "22";
+ }
+ PORT az_be_n
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "byteenable_n";
+ width = "2";
+ }
+ PORT az_cs
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "chipselect";
+ width = "1";
+ }
+ PORT az_data
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "writedata";
+ width = "16";
+ }
+ PORT az_rd_n
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "read_n";
+ width = "1";
+ }
+ PORT az_wr_n
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "write_n";
+ width = "1";
+ }
+ PORT clk
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "clk";
+ width = "1";
+ }
+ PORT reset_n
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "reset_n";
+ width = "1";
+ }
+ PORT za_data
+ {
+ Is_Enabled = "1";
+ direction = "output";
+ type = "readdata";
+ width = "16";
+ }
+ PORT za_valid
+ {
+ Is_Enabled = "1";
+ direction = "output";
+ type = "readdatavalid";
+ width = "1";
+ }
+ PORT za_waitrequest
+ {
+ Is_Enabled = "1";
+ direction = "output";
+ type = "waitrequest";
+ width = "1";
+ }
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Instantiate_In_System_Module = "1";
+ Is_Enabled = "1";
+ Default_Module_Name = "sdram";
+ Disable_Simulation_Port_Wiring = "0";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ View
+ {
+ Settings_Summary = "4194304 x 16<br>
+ Memory size: 8 MBytes<br>
+ 64 MBits
+ ";
+ MESSAGES
+ {
+ }
+ Is_Collapsed = "1";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ register_data_in = "1";
+ sim_model_base = "0";
+ sdram_data_width = "16";
+ sdram_addr_width = "12";
+ sdram_row_width = "12";
+ sdram_col_width = "8";
+ sdram_num_chipselects = "1";
+ sdram_num_banks = "4";
+ refresh_period = "15.625";
+ powerup_delay = "100";
+ cas_latency = "3";
+ t_rfc = "70";
+ t_rp = "20";
+ t_mrd = "3";
+ t_rcd = "20";
+ t_ac = "5.5";
+ t_wr = "14";
+ init_refresh_commands = "2";
+ init_nop_delay = "0";
+ shared_data = "0";
+ starvation_indicator = "0";
+ tristate_bridge_slave = "";
+ is_initialized = "1";
+ sdram_bank_width = "2";
+ }
+ SIMULATION
+ {
+ Fix_Me_Up = "";
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = "az_addr";
+ radix = "hexadecimal";
+ }
+ SIGNAL b
+ {
+ name = "az_be_n";
+ radix = "hexadecimal";
+ }
+ SIGNAL c
+ {
+ name = "az_cs";
+ }
+ SIGNAL d
+ {
+ name = "az_data";
+ radix = "hexadecimal";
+ }
+ SIGNAL e
+ {
+ name = "az_rd_n";
+ }
+ SIGNAL f
+ {
+ name = "az_wr_n";
+ }
+ SIGNAL g
+ {
+ name = "clk";
+ }
+ SIGNAL h
+ {
+ name = "za_data";
+ radix = "hexadecimal";
+ }
+ SIGNAL i
+ {
+ name = "za_valid";
+ }
+ SIGNAL j
+ {
+ name = "za_waitrequest";
+ }
+ SIGNAL k
+ {
+ name = "za_cannotrefresh";
+ suppress = "1";
+ }
+ SIGNAL l
+ {
+ name = "CODE";
+ radix = "ascii";
+ }
+ SIGNAL m
+ {
+ name = "zs_addr";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL n
+ {
+ name = "zs_ba";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL o
+ {
+ name = "zs_cs_n";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL p
+ {
+ name = "zs_ras_n";
+ suppress = "0";
+ }
+ SIGNAL q
+ {
+ name = "zs_cas_n";
+ suppress = "0";
+ }
+ SIGNAL r
+ {
+ name = "zs_we_n";
+ suppress = "0";
+ }
+ SIGNAL s
+ {
+ name = "zs_dq";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL t
+ {
+ name = "zs_dqm";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL u
+ {
+ name = "zt_addr";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL v
+ {
+ name = "zt_ba";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL w
+ {
+ name = "zt_oe";
+ suppress = "1";
+ }
+ SIGNAL x
+ {
+ name = "zt_cke";
+ suppress = "1";
+ }
+ SIGNAL y
+ {
+ name = "zt_chipselect";
+ suppress = "1";
+ }
+ SIGNAL z0
+ {
+ name = "zt_lock_n";
+ suppress = "1";
+ }
+ SIGNAL z1
+ {
+ name = "zt_ras_n";
+ suppress = "1";
+ }
+ SIGNAL z2
+ {
+ name = "zt_cas_n";
+ suppress = "1";
+ }
+ SIGNAL z3
+ {
+ name = "zt_we_n";
+ suppress = "1";
+ }
+ SIGNAL z4
+ {
+ name = "zt_cs_n";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL z5
+ {
+ name = "zt_dqm";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL z6
+ {
+ name = "zt_data";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL z7
+ {
+ name = "tz_data";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL z8
+ {
+ name = "tz_waitrequest";
+ suppress = "1";
+ }
+ }
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.vhd";
+ Synthesis_Only_Files = "";
+ }
+ PORT_WIRING
+ {
+ }
+ }
}
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