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Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Aug 11 20:28:21 CEST 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/08 11:20:28 Modified: jop/quartus/altde2 jop_system.ptf
Log:
tighter SRAM timing
Revision Changes Path
1.2 jop/quartus/altde2/jop_system.ptf
http://www.opencores.org/cvsweb.shtml/jop/quartus/altde2/jop_system.ptf.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: jop_system.ptf
===================================================================
RCS file: /cvsroot/martin/jop/quartus/altde2/jop_system.ptf,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- jop_system.ptf 11 Aug 2006 13:44:45 -0000 1.1
+++ jop_system.ptf 11 Aug 2006 18:28:20 -0000 1.2
@@ -5,7 +5,7 @@
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONE";
- clock_freq = "20000000";
+ clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "1";
do_build_sim = "0";
@@ -15,14 +15,14 @@
{
CLOCK clk
{
- frequency = "20000000";
+ frequency = "50000000";
source = "External";
display_name = "clk";
Is_Clock_Source = "0";
}
}
hdl_language = "vhdl";
- device_family_id = "CYCLONE";
+ device_family_id = "CYCLONEII";
view_master_columns = "1";
view_master_priorities = "0";
name_column_width = "295";
@@ -380,9 +380,9 @@
Data_Width = "16";
Has_Base_Address = "1";
Has_IRQ = "0";
- Setup_Time = "5ns";
- Hold_Time = "5ns";
- Read_Wait_States = "20ns";
+ Setup_Time = "0ns";
+ Hold_Time = "2ns";
+ Read_Wait_States = "18ns";
Write_Wait_States = "10ns";
Read_Latency = "0";
Maximum_Pending_Read_Transactions = "0";
@@ -402,10 +402,10 @@
{
ATS_SETTINGS
{
- Setup_Value = "5";
- Read_Wait_Value = "20";
+ Setup_Value = "0";
+ Read_Wait_Value = "18";
Write_Wait_Value = "10";
- Hold_Value = "5";
+ Hold_Value = "2";
Timing_Units = "ns";
Read_Latency_Value = "0";
Minimum_Arbitration_Shares = "1";
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