OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Sun Jun 25 06:58:57 CEST 2006
Subject: [cvs-checkins] MODIFIED: ethernet_tri_mode ...

Date: 00/06/06 25:06:58

Modified: ethernet_tri_mode/rtl/verilog/MAC_tx MAC_tx_Ctrl.v MAC_tx_FF.v Log: no message Revision Changes Path 1.4 ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: MAC_tx_Ctrl.v =================================================================== RCS file: /cvsroot/maverickist/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- MAC_tx_Ctrl.v 19 Jan 2006 14:07:54 -0000 1.3 +++ MAC_tx_Ctrl.v 25 Jun 2006 04:58:56 -0000 1.4 @@ -39,6 +39,9 @@ // CVS Revision History // // $Log: MAC_tx_Ctrl.v,v $ +// Revision 1.4 2006/06/25 04:58:56 maverickist +// no message +// // Revision 1.3 2006/01/19 14:07:54 maverickist // verification is complete. // @@ -183,6 +186,8 @@ reg TxEn_tmp ; reg [15:0] Tx_pkt_length_rmon ; reg Tx_apply_rmon ; +reg Tx_apply_rmon_tmp ; +reg Tx_apply_rmon_tmp_pl1; reg [2:0] Tx_pkt_err_type_rmon; reg [3:0] RetryCnt ; reg Random_init ; @@ -209,7 +214,6 @@ reg pause_quanta_sub ; reg pause_frame_send_en_dl1 ; reg [15:0] pause_quanta_set_dl1 ; -reg [4:0] send_pause_frame_counter ; reg xoff_gen_complete ; reg xon_gen_complete ; //****************************************************************************** @@ -233,14 +237,6 @@ always @(posedge Clk or posedge Reset) if (Reset) - send_pause_frame_counter <=0; - else if(Current_state!=StateSendPauseFrame) - send_pause_frame_counter <=0; - else - send_pause_frame_counter <=send_pause_frame_counter +1; - -always @(posedge Clk or posedge Reset) - if (Reset) pause_counter <=0; else if (Current_state!=StatePause) pause_counter <=0; @@ -250,9 +246,9 @@ always @(posedge Clk or posedge Reset) if (Reset) IPLengthCounter <=0; - else if (Current_state==StateSwitchNext) + else if (Current_state==StateDefer) IPLengthCounter <=0; - else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StatePAD)) + else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)) IPLengthCounter <=IPLengthCounter+1; always @(posedge Clk or posedge Reset) @@ -279,7 +275,7 @@ StateIFG: if (!FullDuplex&&CRS) Next_state=StateDefer; - else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//È¥µôÒ»Ð©µ¢¸éµÄÊ±¼ä + else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time Next_state=StateIdle; else Next_state=Current_state; @@ -300,7 +296,7 @@ StatePreamble: if (!FullDuplex&&Collision) Next_state=StateJam; - else if ((FullDuplex&&Preamble_counter==7)||(!FullDuplex&&!Collision&&Preamble_counter==7)) + else if ((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6)) Next_state=StateSFD; else Next_state=Current_state; @@ -312,7 +308,7 @@ else Next_state=StateData; StateSendPauseFrame: - if (send_pause_frame_counter==19) + if (IPLengthCounter==17) Next_state=StatePAD; else Next_state=Current_state; @@ -349,8 +345,6 @@ StateFCS: if (!FullDuplex&&Collision) Next_state =StateJam; - else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) - Next_state =StateDefer; else if (CRC_end) Next_state =StateSwitchNext; else @@ -424,7 +418,7 @@ assign Frame_data=TxD_tmp; always @(Current_state) - if (Current_state==StateData||Current_state==StatePAD) + if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD) Data_en =1; else Data_en =0; @@ -486,22 +480,26 @@ else TxD_tmp =Fifo_data; StateSendPauseFrame: - if (Src_MAC_ptr) + if (Src_MAC_ptr&&MAC_tx_add_en) TxD_tmp =MAC_tx_addr_data; else - case (send_pause_frame_counter) - 5'd0: TxD_tmp =8'h01; - 5'd1: TxD_tmp =8'h80; - 5'd2: TxD_tmp =8'hc2; - 5'd3: TxD_tmp =8'h00; - 5'd4: TxD_tmp =8'h00; - 5'd5: TxD_tmp =8'h01; - 5'd12: TxD_tmp =8'h88;//type - 5'd13: TxD_tmp =8'h08;// - 5'd14: TxD_tmp =8'h00;//opcode - 5'd15: TxD_tmp =8'h01; - 5'd16: TxD_tmp =pause_quanta_set_dl1[15:8]; - 5'd17: TxD_tmp =pause_quanta_set_dl1[7:0]; + case (IPLengthCounter) + 7'd0: TxD_tmp =8'h01; + 7'd1: TxD_tmp =8'h80; + 7'd2: TxD_tmp =8'hc2; + 7'd3: TxD_tmp =8'h00; + 7'd4: TxD_tmp =8'h00; + 7'd5: TxD_tmp =8'h01; + 7'd12: TxD_tmp =8'h88;//type + 7'd13: TxD_tmp =8'h08;// + 7'd14: TxD_tmp =8'h00;//opcode + 7'd15: TxD_tmp =8'h01; + 7'd16: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8]; + 7'd17: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0]; +// 7'd60: TxD_tmp =8'h26; +// 7'd61: TxD_tmp =8'h6b; +// 7'd62: TxD_tmp =8'hae; +// 7'd63: TxD_tmp =8'h0a; default:TxD_tmp =0; endcase @@ -533,17 +531,33 @@ Tx_pkt_length_rmon <=0; else if (Current_state==StateSFD) Tx_pkt_length_rmon <=0; - else if (Current_state==StateData) + else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS) Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1; always @ (posedge Clk or posedge Reset) if (Reset) + Tx_apply_rmon_tmp <=0; + else if ((Fifo_eop&&Current_state==StateJamDrop)|| + (Fifo_eop&&Current_state==StateFFEmptyDrop)|| + CRC_end) + Tx_apply_rmon_tmp <=1; + else + Tx_apply_rmon_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon_tmp_pl1 <=0; + else + Tx_apply_rmon_tmp_pl1 <=Tx_apply_rmon_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) Tx_apply_rmon <=0; else if ((Fifo_eop&&Current_state==StateJamDrop)|| (Fifo_eop&&Current_state==StateFFEmptyDrop)|| CRC_end) Tx_apply_rmon <=1; - else + else if (Tx_apply_rmon_tmp_pl1) Tx_apply_rmon <=0; always @ (posedge Clk or posedge Reset) @@ -556,13 +570,13 @@ else if(Fifo_eop&&Fifo_data_err_full) Tx_pkt_err_type_rmon <=3'b011;//overflow else if(CRC_end) - Tx_pkt_err_type_rmon <=3'b100; + Tx_pkt_err_type_rmon <=3'b100;//normal always @ (posedge Clk or posedge Reset) if (Reset) MAC_header_slot_tmp <=0; else if(Current_state==StateSFD&&Next_state==StateData) - MAC_header_slot_tmp <=0; + MAC_header_slot_tmp <=1; else MAC_header_slot_tmp <=0; @@ -578,7 +592,7 @@ else if (Current_state==StateSendPauseFrame) Tx_pkt_type_rmon <=3'b100; else if(MAC_header_slot) - Tx_pkt_type_rmon <={1'b0,TxD_tmp}; + Tx_pkt_type_rmon <={1'b0,TxD[7:6]}; always @(Tx_pkt_length_rmon) 1.5 ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v.diff?r1=1.4&r2=1.5 (In the diff below, changes in quantity of whitespace are not shown.) Index: MAC_tx_FF.v =================================================================== RCS file: /cvsroot/maverickist/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v,v retrieving revision 1.4 retrieving revision 1.5 diff -u -b -r1.4 -r1.5 --- MAC_tx_FF.v 28 May 2006 05:09:20 -0000 1.4 +++ MAC_tx_FF.v 25 Jun 2006 04:58:56 -0000 1.5 @@ -39,6 +39,9 @@ // CVS Revision History // // $Log: MAC_tx_FF.v,v $ +// Revision 1.5 2006/06/25 04:58:56 maverickist +// no message +// // Revision 1.4 2006/05/28 05:09:20 maverickist // no message // @@ -198,6 +201,10 @@ reg Add_rd_reg_rdy_dl2 ; reg [4:0] Tx_Hwmark_pl ; reg [4:0] Tx_Lwmark_pl ; +reg Add_rd_jump_tmp ; +reg Add_rd_jump_tmp_pl1 ; +reg Add_rd_jump ; +reg Add_rd_jump_wr_pl1 ; integer i ; //****************************************************************************** @@ -316,8 +323,14 @@ always @ (posedge Clk_SYS or posedge Reset) if (Reset) - Add_rd_ungray =0; + Add_rd_jump_wr_pl1 <=0; else + Add_rd_jump_wr_pl1 <=Add_rd_jump; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_ungray =0; + else if (!Add_rd_jump_wr_pl1) begin Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1]; for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) @@ -678,6 +691,28 @@ else if (Add_rd_add) Add_rd <= Add_rd + 1; +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump_tmp <=1; + else + Add_rd_jump_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp_pl1 <=0; + else + Add_rd_jump_tmp_pl1 <=Add_rd_jump_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump <=1; + else if (Add_rd_jump_tmp_pl1) + Add_rd_jump <=0; + //gen Fifo_data