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From: cvs at opencores.org<cvs@o...>
Date: Fri Apr 21 04:02:18 CEST 2006
Subject: [cvs-checkins] MODIFIED: mdct ...
Date: 00/06/04 21:04:02

Modified: mdct/source MDCT.VHD ROME.VHD ROMO.VHD
Log:
changed ROM memory model to synchronous


Revision Changes Path
1.2 mdct/source/MDCT.VHD

http://www.opencores.org/cvsweb.shtml/mdct/source/MDCT.VHD.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: MDCT.VHD
===================================================================
RCS file: /cvsroot/mikel262/mdct/source/MDCT.VHD,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- MDCT.VHD 15 Apr 2006 12:57:11 -0000 1.1
+++ MDCT.VHD 21 Apr 2006 02:02:17 -0000 1.2
@@ -190,6 +190,7 @@
component ROME
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
+ clk : in STD_LOGIC;

datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
@@ -201,6 +202,7 @@
component ROMO
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
+ clk : in STD_LOGIC;

datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
@@ -509,6 +511,7 @@
U1_ROME0 : ROME
port map(
addr => romeaddro0_s,
+ clk => clk,

datao => romedatao0_s
);
@@ -519,6 +522,7 @@
U1_ROME1 : ROME
port map(
addr => romeaddro1_s,
+ clk => clk,

datao => romedatao1_s
);
@@ -529,6 +533,7 @@
U1_ROME2 : ROME
port map(
addr => romeaddro2_s,
+ clk => clk,

datao => romedatao2_s
);
@@ -539,6 +544,7 @@
U1_ROME3 : ROME
port map(
addr => romeaddro3_s,
+ clk => clk,

datao => romedatao3_s
);
@@ -548,6 +554,7 @@
U1_ROME4 : ROME
port map(
addr => romeaddro4_s,
+ clk => clk,

datao => romedatao4_s
);
@@ -557,6 +564,7 @@
U1_ROME5 : ROME
port map(
addr => romeaddro5_s,
+ clk => clk,

datao => romedatao5_s
);
@@ -566,6 +574,7 @@
U1_ROME6 : ROME
port map(
addr => romeaddro6_s,
+ clk => clk,

datao => romedatao6_s
);
@@ -575,6 +584,7 @@
U1_ROME7 : ROME
port map(
addr => romeaddro7_s,
+ clk => clk,

datao => romedatao7_s
);
@@ -584,6 +594,7 @@ U1_ROME8 : ROME port map( addr => romeaddro8_s, + clk => clk, datao => romedatao8_s ); @@ -594,6 +605,7 @@ U1_ROMO0 : ROMO port map( addr => romoaddro0_s, + clk => clk, datao => romodatao0_s ); @@ -603,6 +615,7 @@ U1_ROMO1 : ROMO port map( addr => romoaddro1_s, + clk => clk, datao => romodatao1_s ); @@ -612,6 +625,7 @@ U1_ROMO2 : ROMO port map( addr => romoaddro2_s, + clk => clk, datao => romodatao2_s ); @@ -621,6 +635,7 @@ U1_ROMO3 : ROMO port map( addr => romoaddro3_s, + clk => clk, datao => romodatao3_s ); @@ -630,6 +645,7 @@ U1_ROMO4 : ROMO port map( addr => romoaddro4_s, + clk => clk, datao => romodatao4_s ); @@ -639,6 +655,7 @@ U1_ROMO5 : ROMO port map( addr => romoaddro5_s, + clk => clk, datao => romodatao5_s ); @@ -648,6 +665,7 @@ U1_ROMO6 : ROMO port map( addr => romoaddro6_s, + clk => clk, datao => romodatao6_s ); @@ -657,6 +675,7 @@ U1_ROMO7 : ROMO port map( addr => romoaddro7_s, + clk => clk, datao => romodatao7_s ); @@ -666,6 +685,7 @@ U1_ROMO8 : ROMO port map( addr => romoaddro8_s, + clk => clk, datao => romodatao8_s ); @@ -679,6 +699,7 @@ U2_ROME0 : ROME port map( addr => rome2addro0_s, + clk => clk, datao => rome2datao0_s ); @@ -689,6 +710,7 @@ U2_ROME1 : ROME port map( addr => rome2addro1_s, + clk => clk, datao => rome2datao1_s ); @@ -699,6 +721,7 @@ U2_ROME2 : ROME port map( addr => rome2addro2_s, + clk => clk, datao => rome2datao2_s ); @@ -709,6 +732,7 @@ U2_ROME3 : ROME port map( addr => rome2addro3_s, + clk => clk, datao => rome2datao3_s ); @@ -718,6 +742,7 @@ U2_ROME4 : ROME port map( addr => rome2addro4_s, + clk => clk, datao => rome2datao4_s ); @@ -727,6 +752,7 @@ U2_ROME5 : ROME port map( addr => rome2addro5_s, + clk => clk, datao => rome2datao5_s ); @@ -736,6 +762,7 @@ U2_ROME6 : ROME port map( addr => rome2addro6_s, + clk => clk, datao => rome2datao6_s ); @@ -745,6 +772,7 @@ U2_ROME7 : ROME port map( addr => rome2addro7_s, + clk => clk, datao => rome2datao7_s ); @@ -754,6 +782,7 @@ U2_ROME8 : ROME port map( addr => rome2addro8_s, + clk => clk, datao => rome2datao8_s ); @@ -763,6 +792,7 @@ U2_ROME9 : ROME port map( addr => rome2addro9_s, + clk => clk, datao => rome2datao9_s ); @@ -772,6 +802,7 @@ U2_ROME10 : ROME port map( addr => rome2addro10_s, + clk => clk, datao => rome2datao10_s ); @@ -782,6 +813,7 @@ U2_ROMO0 : ROMO port map( addr => romo2addro0_s, + clk => clk, datao => romo2datao0_s ); @@ -791,6 +823,7 @@ U2_ROMO1 : ROMO port map( addr => romo2addro1_s, + clk => clk, datao => romo2datao1_s ); @@ -800,6 +833,7 @@ U2_ROMO2 : ROMO port map( addr => romo2addro2_s, + clk => clk, datao => romo2datao2_s ); @@ -809,6 +843,7 @@ U2_ROMO3 : ROMO port map( addr => romo2addro3_s, + clk => clk, datao => romo2datao3_s ); @@ -818,6 +853,7 @@ U2_ROMO4 : ROMO port map( addr => romo2addro4_s, + clk => clk, datao => romo2datao4_s ); @@ -827,6 +863,7 @@ U2_ROMO5 : ROMO port map( addr => romo2addro5_s, + clk => clk, datao => romo2datao5_s ); @@ -836,6 +873,7 @@ U2_ROMO6 : ROMO port map( addr => romo2addro6_s, + clk => clk, datao => romo2datao6_s ); @@ -845,6 +883,7 @@ U2_ROMO7 : ROMO port map( addr => romo2addro7_s, + clk => clk, datao => romo2datao7_s ); @@ -854,6 +893,7 @@ U2_ROMO8 : ROMO port map( addr => romo2addro8_s, + clk => clk, datao => romo2datao8_s ); @@ -863,6 +903,7 @@ U2_ROMO9 : ROMO port map( addr => romo2addro9_s, + clk => clk, datao => romo2datao9_s ); @@ -872,6 +913,7 @@ U2_ROMO10 : ROMO port map( addr => romo2addro10_s, + clk => clk, datao => romo2datao10_s ); 1.2 mdct/source/ROME.VHD http://www.opencores.org/cvsweb.shtml/mdct/source/ROME.VHD.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: ROME.VHD =================================================================== RCS file: /cvsroot/mikel262/mdct/source/ROME.VHD,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- ROME.VHD 15 Apr 2006 12:57:12 -0000 1.1 +++ ROME.VHD 21 Apr 2006 02:02:17 -0000 1.2 @@ -32,6 +32,7 @@ entity ROME is port( addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); + clk : in STD_LOGIC; datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0) ); @@ -115,16 +116,19 @@ std_logic_vector( CP ), (others => '0') ); - + signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); begin - process( addr ) + datao <= rom( TO_INTEGER(UNSIGNED(addr_reg)) ); + + process(clk) begin - datao <= rom( TO_INTEGER(UNSIGNED(addr)) ); + if clk = '1' and clk'event then + addr_reg <= addr; + end if; end process; - end RTL; -------------------------------------------------------------------------------- 1.2 mdct/source/ROMO.VHD http://www.opencores.org/cvsweb.shtml/mdct/source/ROMO.VHD.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: ROMO.VHD =================================================================== RCS file: /cvsroot/mikel262/mdct/source/ROMO.VHD,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- ROMO.VHD 15 Apr 2006 12:57:12 -0000 1.1 +++ ROMO.VHD 21 Apr 2006 02:02:17 -0000 1.2 @@ -32,6 +32,7 @@ entity ROMO is port( addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); + clk : in STD_LOGIC; datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0) ); @@ -111,14 +112,17 @@ std_logic_vector( GP+FM+EP ), std_logic_vector( GP+FM+EP+DM ) ); + + signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); begin - ------------------------------------------------------------------------------- - rom_proc: -- ROM generator process - ------------------------------------------------------------------------------- - process( addr ) + datao <= rom( TO_INTEGER(UNSIGNED(addr_reg)) ); + + process(clk) begin - datao <= rom( TO_INTEGER(UNSIGNED(addr)) ); + if clk = '1' and clk'event then + addr_reg <= addr; + end if; end process; end RTL;