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From: cvs at opencores.org<cvs@o...>
Date: Tue Dec 20 12:32:22 CET 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/12 20:12:32

Added: or1k/rc203soc/sw/uClinux/include/asm-sparc a.out.h asi.h
asmmacro.h atomic.h atops.h auxio.h bitops.h
bsderrno.h bugs.h byteorder.h cache.h checksum.h
clock.h contregs.h cprefix.h cypress.h delay.h
dma.h ecc.h eeprom.h elf.h errno.h fbio.h fcntl.h
floppy.h head.h idprom.h io.h ioctl.h ioctls.h
iommu.h irq.h kbio.h kdebug.h kgdb.h machines.h
mbus.h memreg.h mman.h mmu_context.h mostek.h
mpmbox.h msi.h mxcc.h openprom.h oplib.h page.h
param.h pconf.h pgtable.h pgtsrmmu.h pgtsun4.h
pgtsun4c.h posix_types.h processor.h psr.h ptrace.h
resource.h ross.h sbus.h segment.h shmparam.h
sigcontext.h signal.h smp.h smp_lock.h smpprim.h
socket.h sockios.h solerrno.h stat.h statfs.h
string.h swift.h sysen.h system.h termbits.h
termios.h timer.h traps.h tsunami.h types.h ultra.h
unistd.h user.h vac-ops.h vaddrs.h viking.h
vuid_event.h winmacro.h
Log:
First Import of RC20x uClinux


Revision Changes Path
1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/a.out.h

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/a.out.h?rev=1.1&content-type=text/x-cvsweb-markup

Index: a.out.h
===================================================================
/* $Id: a.out.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */
#ifndef __SPARC_A_OUT_H__
#define __SPARC_A_OUT_H__

#define SPARC_PGSIZE 0x2000 /* Thanks to the sun4 architecture... */
#define SEGMENT_SIZE SPARC_PGSIZE /* whee... */

struct exec {
unsigned char a_dynamic:1; /* A __DYNAMIC is in this image */
unsigned char a_toolversion:7;
unsigned char a_machtype;
unsigned short a_info;
unsigned long a_text; /* length of text, in bytes */
unsigned long a_data; /* length of data, in bytes */
unsigned long a_bss; /* length of bss, in bytes */
unsigned long a_syms; /* length of symbol table, in bytes */
unsigned long a_entry; /* where program begins */
unsigned long a_trsize;
unsigned long a_drsize;
};

/* Where in the file does the text information begin? */
#define N_TXTOFF(x) (N_MAGIC(x) == ZMAGIC ? 0 : sizeof (struct exec))

/* Where do the Symbols start? */
#define N_SYMOFF(x) (N_TXTOFF(x) + (x).a_text + \
(x).a_data + (x).a_trsize + \
(x).a_drsize)

/* Where does text segment go in memory after being loaded? */
#define N_TXTADDR(x) (((N_MAGIC(x) == ZMAGIC) && \
((x).a_entry < SPARC_PGSIZE)) ? \
0 : SPARC_PGSIZE)

/* And same for the data segment.. */
#define N_DATADDR(x) (N_MAGIC(x)==OMAGIC ? \
(N_TXTADDR(x) + (x).a_text) \
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))

#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)

#ifdef __KERNEL__

#define STACK_TOP TASK_SIZE

#endif

#endif /* __SPARC_A_OUT_H__ */



1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/asi.h

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/asi.h?rev=1.1&content-type=text/x-cvsweb-markup

Index: asi.h
===================================================================
/* $Id: asi.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */
#ifndef _SPARC_ASI_H
#define _SPARC_ASI_H

/* asi.h: Address Space Identifier values for the sparc.
*
* Copyright (C) 1995 David S. Miller (davem@c...)
*
* Pioneer work for sun4m: Paul Hatchman (paul@s...)
* Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@i...>
*/

/* The first batch are for the sun4c. */ #define ASI_NULL1 0x00 #define ASI_NULL2 0x01 /* sun4c and sun4 control registers and mmu/vac ops */ #define ASI_CONTROL 0x02 #define ASI_SEGMAP 0x03 #define ASI_PTE 0x04 #define ASI_HWFLUSHSEG 0x05 #define ASI_HWFLUSHPAGE 0x06 #define ASI_REGMAP 0x06 #define ASI_HWFLUSHCONTEXT 0x07 #define ASI_USERTXT 0x08 #define ASI_KERNELTXT 0x09 #define ASI_USERDATA 0x0a #define ASI_KERNELDATA 0x0b /* VAC Cache flushing on sun4c and sun4 */ #define ASI_FLUSHSEG 0x0c #define ASI_FLUSHPG 0x0d #define ASI_FLUSHCTX 0x0e /* SPARCstation-5: only 6 bits are decoded. */ /* wo = Write Only, rw = Read Write; */ /* ss = Single Size, as = All Sizes; */ #define ASI_M_RES00 0x00 /* Don't touch... */ #define ASI_M_UNA01 0x01 /* Same here... */ #define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */ #define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */ #define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */ #define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */ #define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */ #define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */ #define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */ #define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */ #define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */ #define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */ #define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */ #define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */ #define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */ #define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */ /* The following cache flushing ASIs work only with the 'sta' * instruction. Results are unpredictable for 'swap' and 'ldstuba', * so don't do it. */ /* These ASI flushes affect external caches too. */ #define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */ #define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */ #define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */ #define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */ #define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */ /* Block-copy operations are available only on certain V8 cpus. */ #define ASI_M_BCOPY 0x17 /* Block copy */ /* These affect only the ICACHE and are Ross HyperSparc specific. */ #define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */ #define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */ #define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */ #define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */ #define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */ /* Block-fill operations are available on certain V8 cpus */ #define ASI_M_BFILL 0x1F /* This allows direct access to main memory, actually 0x20 to 0x2f are * the available ASI's for physical ram pass-through, but I don't have * any idea what the other ones do.... */ #define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */ #define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */ #define ASI_M_VMEUS 0x2A /* VME user 16-bit access */ #define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */ #define ASI_M_VMEUT 0x2C /* VME user 32-bit access */ #define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */ #define ASI_M_SBUS 0x2E /* Direct SBus access */ #define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */ /* This is ROSS HyperSparc only. */ #define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */ /* Tsunami/Viking i/d cache flash clear. */ #define ASI_M_IC_FLCLEAR 0x36 #define ASI_M_DC_FLCLEAR 0x37 #define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */ #define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */ #endif /* _SPARC_ASI_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/asmmacro.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/asmmacro.h?rev=1.1&content-type=text/x-cvsweb-markup Index: asmmacro.h =================================================================== /* asmmacro.h: Assembler macros. * * Copyright (C) 1996 David S. Miller (davem@c...) */ #ifndef _SPARC_ASMMACRO_H #define _SPARC_ASMMACRO_H /* #define SMP_DEBUG */ #define GET_PROCESSOR_ID(reg) \ rd %tbr, %reg; \ srl %reg, 12, %reg; \ and %reg, 3, %reg; #define GET_PROCESSOR_MID(reg, tmp) \ GET_PROCESSOR_ID(reg) \ set C_LABEL(mid_xlate), %tmp; \ ldub [%tmp + %reg], %reg; #define GET_PROCESSOR_OFFSET(reg) \ rd %tbr, %reg; \ srl %reg, 10, %reg; \ and %reg, 0xc, %reg; #define PROCESSOR_OFFSET_TO_ID(reg) \ srl %reg, 2, %reg; #define PROCESSOR_ID_TO_OFFSET(reg) \ sll %reg, 2, %reg; /* All trap entry points _must_ begin with this macro or else you * lose. It makes sure the kernel has a proper window so that * c-code can be called. */ #ifndef SMP_DEBUG #define SAVE_ALL \ sethi %hi(trap_setup), %l4; \ jmpl %l4 + %lo(trap_setup), %l6; \ nop; #else #define SAVE_ALL \ GET_PROCESSOR_ID(l4); \ set C_LABEL(trap_log), %l5; \ sll %l4, 11, %l6; \ add %l5, %l6, %l5; \ set C_LABEL(trap_log_ent), %l6; \ sll %l4, 2, %l4; \ add %l6, %l4, %l6; \ ld [%l6], %l6; \ sll %l6, 3, %l6; \ st %l1, [%l5 + %l6]; \ add %l5, 4, %l5; \ st %l0, [%l5 + %l6]; \ set C_LABEL(trap_log_ent), %l5; \ add %l5, %l4, %l5; \ srl %l6, 3, %l6; \ add %l6, 1, %l6; \ and %l6, 255, %l6; \ st %l6, [%l5]; \ sethi %hi(trap_setup), %l4; \ jmpl %l4 + %lo(trap_setup), %l6; \ nop; #endif /* All traps low-level code here must end with this macro. * For SMP configurations the ret_trap_entry routine will * have to appropriate code to actually release the kernel * entry lock. */ #define RESTORE_ALL \ b ret_trap_entry; \ nop; #ifndef __SMP__ #define ENTER_SYSCALL #define LEAVE_SYSCALL #define ENTER_IRQ #define LEAVE_IRQ #else #define INCREMENT_COUNTER(symbol, tmp1, tmp2) \ set C_LABEL(symbol), %tmp1; \ ld [%tmp1], %tmp2; \ add %tmp2, 1, %tmp2; \ st %tmp2, [%tmp1]; #define DECREMENT_COUNTER(symbol, tmp1, tmp2) \ set C_LABEL(symbol), %tmp1; \ ld [%tmp1], %tmp2; \ sub %tmp2, 1, %tmp2; \ st %tmp2, [%tmp1]; /* This is so complicated I suggest you don't look at it. */ #define ENTER_MASK(mask) \ GET_PROCESSOR_OFFSET(l4) \ set C_LABEL(smp_spinning), %l6; \ add %l6, %l4, %l6; \ mov 1, %l5; \ st %l5, [%l6]; \ set C_LABEL(smp_proc_in_lock), %l5; \ ld [%l5 + %l4], %l6; \ or %l6, mask, %l6; \ st %l6, [%l5 + %l4]; \ 1: \ set C_LABEL(kernel_flag), %l5; \ ldstub [%l5], %l6; \ cmp %l6, 0; \ be 3f; \ nop; \ set C_LABEL(active_kernel_processor), %l5; \ GET_PROCESSOR_ID(l4) \ ldub [%l5], %l6; \ cmp %l6, %l4; \ be 4f; \ nop; \ 2: \ GET_PROCESSOR_MID(l4, l5) \ set C_LABEL(sun4m_interrupts), %l5; \ ld [%l5], %l5; \ sll %l4, 12, %l4; \ add %l5, %l4, %l5; \ ld [%l5], %l4; \ sethi %hi(0x80000000), %l6; \ andcc %l6, %l4, %g0; \ be 5f; \ nop; \ st %l6, [%l5 + 4]; \ nop; nop; nop; \ ld [%l5], %g0; \ nop; nop; nop; \ or %l0, PSR_PIL, %l4; \ wr %l4, 0x0, %psr; \ nop; nop; nop; \ wr %l4, PSR_ET, %psr; \ nop; nop; nop; \ call C_LABEL(smp_message_irq); \ nop; \ wr %l0, 0x0, %psr; \ nop; nop; nop; \ 5: \ set C_LABEL(kernel_flag), %l5; \ ldub [%l5], %l6; \ cmp %l6, 0; \ bne 2b; \ nop; \ b 1b; \ nop; \ 3: \ GET_PROCESSOR_ID(l4) \ set C_LABEL(active_kernel_processor), %l5; \ stb %l4, [%l5]; \ GET_PROCESSOR_MID(l4, l5) \ set C_LABEL(irq_rcvreg), %l5; \ ld [%l5], %l5; \ st %l4, [%l5]; \ 4: \ GET_PROCESSOR_OFFSET(l4) \ set C_LABEL(smp_spinning), %l6; \ st %g0, [%l6 + %l4]; #define ENTER_SYSCALL \ ENTER_MASK(SMP_FROM_SYSCALL) \ INCREMENT_COUNTER(kernel_counter, l6, l5) \ INCREMENT_COUNTER(syscall_count, l6, l5) #define ENTER_IRQ \ ENTER_MASK(SMP_FROM_INT) \ INCREMENT_COUNTER(kernel_counter, l6, l5) #define LEAVE_MASK(mask) \ GET_PROCESSOR_OFFSET(l4) \ set C_LABEL(smp_proc_in_lock), %l5; \ ld [%l5 + %l4], %l6; \ andn %l6, mask, %l6; \ st %l6, [%l5 + %l4]; #define LEAVE_SYSCALL \ LEAVE_MASK(SMP_FROM_SYSCALL) \ DECREMENT_COUNTER(syscall_count, l6, l5) \ set C_LABEL(kernel_counter), %l6; \ ld [%l6], %l5; \ subcc %l5, 1, %l5; \ st %l5, [%l6]; \ bne 1f; \ nop; \ set C_LABEL(active_kernel_processor), %l6; \ mov NO_PROC_ID, %l5; \ stb %l5, [%l6]; \ set C_LABEL(kernel_flag), %l6; \ stb %g0, [%l6]; \ 1: #define LEAVE_IRQ \ LEAVE_MASK(SMP_FROM_INT) \ INCREMENT_COUNTER(syscall_count, l6, l5) #define RESTORE_ALL_FASTIRQ \ b ret_irq_entry; \ nop; #endif /* !(__SMP__) */ #endif /* !(_SPARC_ASMMACRO_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/atomic.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/atomic.h?rev=1.1&content-type=text/x-cvsweb-markup Index: atomic.h =================================================================== /* atomic.h: These really suck for now. * * Copyright (C) 1996 David S. Miller (davem@c...) */ #ifndef __ARCH_SPARC_ATOMIC__ #define __ARCH_SPARC_ATOMIC__ #ifdef __SMP__ #include <asm/smp.h> #include <asm/smp_lock.h> #endif typedef int atomic_t; static __inline__ void atomic_add(atomic_t i, atomic_t *v) { unsigned long flags; save_flags(flags); cli(); *v += i; restore_flags(flags); } static __inline__ void atomic_sub(atomic_t i, atomic_t *v) { unsigned long flags; save_flags(flags); cli(); *v -= i; restore_flags(flags); } static __inline__ int atomic_sub_and_test(atomic_t i, atomic_t *v) { unsigned long flags, result; save_flags(flags); cli(); *v -= i; result = (*v == 0); restore_flags(flags); return result; } static __inline__ void atomic_inc(atomic_t *v) { atomic_add(1, v); } static __inline__ void atomic_dec(atomic_t *v) { atomic_sub(1, v); } static __inline__ int atomic_dec_and_test(atomic_t *v) { return atomic_sub_and_test(1, v); } #endif /* !(__ARCH_SPARC_ATOMIC__) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/atops.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/atops.h?rev=1.1&content-type=text/x-cvsweb-markup Index: atops.h =================================================================== /* atops.h: Atomic SPARC operations. * * Copyright (C) 1996 David S. Miller (davem@c...) */ #ifndef _SPARC_ATOPS_H #define _SPARC_ATOPS_H #ifdef __SMP__ extern __inline volatile unsigned char ldstub(volatile unsigned char *lock) { volatile unsigned char retval; __asm__ __volatile__("ldstub [%1], %0\n\t" : "=&r" (retval) : "r" (lock)); return retval; } #endif #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/auxio.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/auxio.h?rev=1.1&content-type=text/x-cvsweb-markup Index: auxio.h =================================================================== /* $Id: auxio.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * auxio.h: Definitions and code for the Auxiliary I/O register. * * Copyright (C) 1995 David S. Miller (davem@c...) */ #ifndef _SPARC_AUXIO_H #define _SPARC_AUXIO_H #include <asm/system.h> #include <asm/vaddrs.h> extern unsigned char *auxio_register; /* This register is an unsigned char in IO space. It does two things. * First, it is used to control the front panel LED light on machines * that have it (good for testing entry points to trap handlers and irq's) * Secondly, it controls various floppy drive parameters. */ #define AUXIO_ORMEIN 0xf0 /* All writes must set these bits. */ #define AUXIO_ORMEIN4M 0xc0 /* sun4m - All writes must set these bits. */ #define AUXIO_FLPY_DENS 0x20 /* Floppy density, high if set. Read only. */ #define AUXIO_FLPY_DCHG 0x10 /* A disk change occurred. Read only. */ #define AUXIO_EDGE_ON 0x10 /* sun4m - On means Jumper block is in. */ #define AUXIO_FLPY_DSEL 0x08 /* Drive select/start-motor. Write only. */ /* Set the following to one, then zero, after doing a pseudo DMA transfer. */ #define AUXIO_FLPY_TCNT 0x04 /* Floppy terminal count. Write only. */ /* Set the following to zero to eject the floppy. */ #define AUXIO_FLPY_EJCT 0x02 /* Eject floppy disk. Write only. */ #define AUXIO_LED 0x01 /* On if set, off if unset. Read/Write */ #define AUXREG ((volatile unsigned char *)(auxio_register)) #define TURN_ON_LED *AUXREG = (*AUXREG | AUXIO_ORMEIN | AUXIO_LED) #define TURN_OFF_LED *AUXREG = ((*AUXREG | AUXIO_ORMEIN) & (~AUXIO_LED)) #define FLIP_LED *AUXREG = ((*AUXREG | AUXIO_ORMEIN) ^ AUXIO_LED) #define FLPY_MOTORON *AUXREG = ((*AUXREG | AUXIO_ORMEIN) | AUXIO_FLPY_DSEL) #define FLPY_MOTOROFF *AUXREG = ((*AUXREG | AUXIO_ORMEIN) & (~AUXIO_FLPY_DSEL)) #define FLPY_TCNTON *AUXREG = ((*AUXREG | AUXIO_ORMEIN) | AUXIO_FLPY_TCNT) #define FLPY_TCNTOFF *AUXREG = ((*AUXREG | AUXIO_ORMEIN) & (~AUXIO_FLPY_TCNT)) #ifndef __ASSEMBLY__ extern inline void set_auxio(unsigned char bits_on, unsigned char bits_off) { unsigned char regval; unsigned long flags; save_flags(flags); cli(); switch(sparc_cpu_model) { case sun4c: regval = *AUXREG; *AUXREG = ((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN; break; case sun4m: regval = *AUXREG; *AUXREG = ((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M; break; default: panic("Can't set AUXIO register on this machine."); }; restore_flags(flags); } #endif /* !(__ASSEMBLY__) */ #endif /* !(_SPARC_AUXIO_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/bitops.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/bitops.h?rev=1.1&content-type=text/x-cvsweb-markup Index: bitops.h =================================================================== /* $Id: bitops.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * bitops.h: Bit string operations on the Sparc. * * Copyright 1995, David S. Miller (davem@c...). */ #ifndef _SPARC_BITOPS_H #define _SPARC_BITOPS_H #include <linux/kernel.h> #ifdef __KERNEL__ #include <asm/system.h> #endif #ifdef __SMP__ #define SMPVOL volatile #else #define SMPVOL #endif /* Set bit 'nr' in 32-bit quantity at address 'addr' where bit '0' * is in the highest of the four bytes and bit '31' is the high bit * within the first byte. Sparc is BIG-Endian. Unless noted otherwise * all bit-ops return 0 if bit was previously clear and != 0 otherwise. */ extern __inline__ unsigned long set_bit(unsigned long nr, SMPVOL void *addr) { int mask, flags; unsigned long *ADDR = (unsigned long *) addr; unsigned long oldbit; ADDR += nr >> 5; mask = 1 << (nr & 31); save_flags(flags); cli(); oldbit = (mask & *ADDR); *ADDR |= mask; restore_flags(flags); return oldbit != 0; } extern __inline__ unsigned long clear_bit(unsigned long nr, SMPVOL void *addr) { int mask, flags; unsigned long *ADDR = (unsigned long *) addr; unsigned long oldbit; ADDR += nr >> 5; mask = 1 << (nr & 31); save_flags(flags); cli(); oldbit = (mask & *ADDR); *ADDR &= ~mask; restore_flags(flags); return oldbit != 0; } extern __inline__ unsigned long change_bit(unsigned long nr, SMPVOL void *addr) { int mask, flags; unsigned long *ADDR = (unsigned long *) addr; unsigned long oldbit; ADDR += nr >> 5; mask = 1 << (nr & 31); save_flags(flags); cli(); oldbit = (mask & *ADDR); *ADDR ^= mask; restore_flags(flags); return oldbit != 0; } /* The following routine need not be atomic. */ extern __inline__ unsigned long test_bit(int nr, const SMPVOL void *addr) { return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0; } /* The easy/cheese version for now. */ extern __inline__ unsigned long ffz(unsigned long word) { unsigned long result = 0; while(word & 1) { result++; word >>= 1; } return result; } /* find_next_zero_bit() finds the first zero bit in a bit string of length * 'size' bits, starting the search at bit 'offset'. This is largely based * on Linus's ALPHA routines, which are pretty portable BTW. */ extern __inline__ unsigned long find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; if (offset >= size) return size; size -= result; offset &= 31UL; if (offset) { tmp = *(p++); tmp |= ~0UL >> (32-offset); if (size < 32) goto found_first; if (~tmp) goto found_middle; size -= 32; result += 32; } while (size & ~31UL) { if (~(tmp = *(p++))) goto found_middle; result += 32; size -= 32; } if (!size) return result; tmp = *p; found_first: tmp |= ~0UL >> size; found_middle: return result + ffz(tmp); } /* Linus sez that gcc can optimize the following correctly, we'll see if this * holds on the Sparc as it does for the ALPHA. */ #define find_first_zero_bit(addr, size) \ find_next_zero_bit((addr), (size), 0) /* Now for the ext2 filesystem bit operations and helper routines. */ extern __inline__ int ext2_set_bit(int nr,void * addr) { int mask, retval, flags; unsigned char *ADDR = (unsigned char *) addr; ADDR += nr >> 3; mask = 1 << (nr & 0x07); save_flags(flags); cli(); retval = (mask & *ADDR) != 0; *ADDR |= mask; restore_flags(flags); return retval; } extern __inline__ int ext2_clear_bit(int nr, void * addr) { int mask, retval, flags; unsigned char *ADDR = (unsigned char *) addr; ADDR += nr >> 3; mask = 1 << (nr & 0x07); save_flags(flags); cli(); retval = (mask & *ADDR) != 0; *ADDR &= ~mask; restore_flags(flags); return retval; } extern __inline__ int ext2_test_bit(int nr, const void * addr) { int mask; const unsigned char *ADDR = (const unsigned char *) addr; ADDR += nr >> 3; mask = 1 << (nr & 0x07); return ((mask & *ADDR) != 0); } #define ext2_find_first_zero_bit(addr, size) \ ext2_find_next_zero_bit((addr), (size), 0) extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; if (offset >= size) return size; size -= result; offset &= 31UL; if(offset) { tmp = *(p++); tmp |= ~0UL << (32-offset); if(size < 32) goto found_first; if(~tmp) goto found_middle; size -= 32; result += 32; } while(size & ~31UL) { if(~(tmp = *(p++))) goto found_middle; result += 32; size -= 32; } if(!size) return result; tmp = *p; found_first: tmp |= ~0UL << size; found_middle: tmp = ((tmp>>24) | ((tmp>>8)&0xff00) | ((tmp<<8)&0xff0000) | (tmp<<24)); return result + ffz(tmp); } #endif /* defined(_SPARC_BITOPS_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/bsderrno.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/bsderrno.h?rev=1.1&content-type=text/x-cvsweb-markup Index: bsderrno.h =================================================================== /* $Id: bsderrno.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * bsderrno.h: Error numbers for NetBSD binary compatibility * * Copyright (C) 1995 David S. Miller (davem@c...) */ #ifndef _SPARC_BSDERRNO_H #define _SPARC_BSDERRNO_H #define BSD_EPERM 1 /* Operation not permitted */ #define BSD_ENOENT 2 /* No such file or directory */ #define BSD_ESRCH 3 /* No such process */ #define BSD_EINTR 4 /* Interrupted system call */ #define BSD_EIO 5 /* Input/output error */ #define BSD_ENXIO 6 /* Device not configured */ #define BSD_E2BIG 7 /* Argument list too long */ #define BSD_ENOEXEC 8 /* Exec format error */ #define BSD_EBADF 9 /* Bad file descriptor */ #define BSD_ECHILD 10 /* No child processes */ #define BSD_EDEADLK 11 /* Resource deadlock avoided */ #define BSD_ENOMEM 12 /* Cannot allocate memory */ #define BSD_EACCES 13 /* Permission denied */ #define BSD_EFAULT 14 /* Bad address */ #define BSD_ENOTBLK 15 /* Block device required */ #define BSD_EBUSY 16 /* Device busy */ #define BSD_EEXIST 17 /* File exists */ #define BSD_EXDEV 18 /* Cross-device link */ #define BSD_ENODEV 19 /* Operation not supported by device */ #define BSD_ENOTDIR 20 /* Not a directory */ #define BSD_EISDIR 21 /* Is a directory */ #define BSD_EINVAL 22 /* Invalid argument */ #define BSD_ENFILE 23 /* Too many open files in system */ #define BSD_EMFILE 24 /* Too many open files */ #define BSD_ENOTTY 25 /* Inappropriate ioctl for device */ #define BSD_ETXTBSY 26 /* Text file busy */ #define BSD_EFBIG 27 /* File too large */ #define BSD_ENOSPC 28 /* No space left on device */ #define BSD_ESPIPE 29 /* Illegal seek */ #define BSD_EROFS 30 /* Read-only file system */ #define BSD_EMLINK 31 /* Too many links */ #define BSD_EPIPE 32 /* Broken pipe */ #define BSD_EDOM 33 /* Numerical argument out of domain */ #define BSD_ERANGE 34 /* Result too large */ #define BSD_EAGAIN 35 /* Resource temporarily unavailable */ #define BSD_EWOULDBLOCK EAGAIN /* Operation would block */ #define BSD_EINPROGRESS 36 /* Operation now in progress */ #define BSD_EALREADY 37 /* Operation already in progress */ #define BSD_ENOTSOCK 38 /* Socket operation on non-socket */ #define BSD_EDESTADDRREQ 39 /* Destination address required */ #define BSD_EMSGSIZE 40 /* Message too long */ #define BSD_EPROTOTYPE 41 /* Protocol wrong type for socket */ #define BSD_ENOPROTOOPT 42 /* Protocol not available */ #define BSD_EPROTONOSUPPORT 43 /* Protocol not supported */ #define BSD_ESOCKTNOSUPPORT 44 /* Socket type not supported */ #define BSD_EOPNOTSUPP 45 /* Operation not supported */ #define BSD_EPFNOSUPPORT 46 /* Protocol family not supported */ #define BSD_EAFNOSUPPORT 47 /* Address family not supported by protocol family */ #define BSD_EADDRINUSE 48 /* Address already in use */ #define BSD_EADDRNOTAVAIL 49 /* Can't assign requested address */ #define BSD_ENETDOWN 50 /* Network is down */ #define BSD_ENETUNREACH 51 /* Network is unreachable */ #define BSD_ENETRESET 52 /* Network dropped connection on reset */ #define BSD_ECONNABORTED 53 /* Software caused connection abort */ #define BSD_ECONNRESET 54 /* Connection reset by peer */ #define BSD_ENOBUFS 55 /* No buffer space available */ #define BSD_EISCONN 56 /* Socket is already connected */ #define BSD_ENOTCONN 57 /* Socket is not connected */ #define BSD_ESHUTDOWN 58 /* Can't send after socket shutdown */ #define BSD_ETOOMANYREFS 59 /* Too many references: can't splice */ #define BSD_ETIMEDOUT 60 /* Operation timed out */ #define BSD_ECONNREFUSED 61 /* Connection refused */ #define BSD_ELOOP 62 /* Too many levels of symbolic links */ #define BSD_ENAMETOOLONG 63 /* File name too long */ #define BSD_EHOSTDOWN 64 /* Host is down */ #define BSD_EHOSTUNREACH 65 /* No route to host */ #define BSD_ENOTEMPTY 66 /* Directory not empty */ #define BSD_EPROCLIM 67 /* Too many processes */ #define BSD_EUSERS 68 /* Too many users */ #define BSD_EDQUOT 69 /* Disc quota exceeded */ #define BSD_ESTALE 70 /* Stale NFS file handle */ #define BSD_EREMOTE 71 /* Too many levels of remote in path */ #define BSD_EBADRPC 72 /* RPC struct is bad */ #define BSD_ERPCMISMATCH 73 /* RPC version wrong */ #define BSD_EPROGUNAVAIL 74 /* RPC prog. not avail */ #define BSD_EPROGMISMATCH 75 /* Program version wrong */ #define BSD_EPROCUNAVAIL 76 /* Bad procedure for program */ #define BSD_ENOLCK 77 /* No locks available */ #define BSD_ENOSYS 78 /* Function not implemented */ #define BSD_EFTYPE 79 /* Inappropriate file type or format */ #define BSD_EAUTH 80 /* Authentication error */ #define BSD_ENEEDAUTH 81 /* Need authenticator */ #define BSD_ELAST 81 /* Must be equal largest errno */ #endif /* !(_SPARC_BSDERRNO_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/bugs.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/bugs.h?rev=1.1&content-type=text/x-cvsweb-markup Index: bugs.h =================================================================== /* $Id: bugs.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * include/asm-sparc/bugs.h: Sparc probes for various bugs. * * Copyright (C) 1994 David S. Miller (davem@c...) */ static void check_bugs(void) { } 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/byteorder.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/byteorder.h?rev=1.1&content-type=text/x-cvsweb-markup Index: byteorder.h =================================================================== /* $Id: byteorder.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */ #ifndef _SPARC_BYTEORDER_H #define _SPARC_BYTEORDER_H #define ntohl(x) x #define ntohs(x) x #define htonl(x) x #define htons(x) x #ifdef __KERNEL__ #define __BIG_ENDIAN #endif #define __BIG_ENDIAN_BITFIELD #endif /* !(_SPARC_BYTEORDER_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/cache.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/cache.h?rev=1.1&content-type=text/x-cvsweb-markup Index: cache.h =================================================================== /* $Id: cache.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * cache.h: Cache specific code for the Sparc. These include flushing * and direct tag/data line access. * * Copyright (C) 1995 David S. Miller (davem@c...) */ #ifndef _SPARC_CACHE_H #define _SPARC_CACHE_H #include <asm/asi.h> /* Direct access to the instruction cache is provided through and * alternate address space. The IDC bit must be off in the ICCR on * HyperSparcs for these accesses to work. The code below does not do * any checking, the caller must do so. These routines are for * diagnostics only, but could end up being useful. Use with care. * Also, you are asking for trouble if you execute these in one of the * three instructions following a %asr/%psr access or modification. */ /* First, cache-tag access. */ extern inline unsigned int get_icache_tag(int setnum, int tagnum) { unsigned int vaddr, retval; vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5); __asm__ __volatile__("lda [%1] %2, %0\n\t" : "=r" (retval) : "r" (vaddr), "i" (ASI_M_TXTC_TAG)); return retval; } extern inline void put_icache_tag(int setnum, int tagnum, unsigned int entry) { unsigned int vaddr; vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5); __asm__ __volatile__("sta %0, [%1] %2\n\t" : : "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) : "memory"); } /* Second cache-data access. The data is returned two-32bit quantities * at a time. */ extern inline void get_icache_data(int setnum, int tagnum, int subblock, unsigned int *data) { unsigned int value1, value2, vaddr; vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) | ((subblock&0x3) << 3); __asm__ __volatile__("ldda [%2] %3, %%g2\n\t" "or %%g0, %%g2, %0\n\t" "or %%g0, %%g3, %1\n\t" : "=r" (value1), "=r" (value2) : "r" (vaddr), "i" (ASI_M_TXTC_DATA) : "g2", "g3"); data[0] = value1; data[1] = value2; } extern inline void put_icache_data(int setnum, int tagnum, int subblock, unsigned int *data) { unsigned int value1, value2, vaddr; vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) | ((subblock&0x3) << 3); value1 = data[0]; value2 = data[1]; __asm__ __volatile__("or %%g0, %0, %%g2\n\t" "or %%g0, %1, %%g3\n\t" "stda %%g2, [%2] %3\n\t" : : "r" (value1), "r" (value2), "r" (vaddr), "i" (ASI_M_TXTC_DATA) : "g2", "g3", "memory" /* no joke */); } /* Different types of flushes with the ICACHE. Some of the flushes * affect both the ICACHE and the external cache. Others only clear * the ICACHE entries on the cpu itself. V8's (most) allow * granularity of flushes on the packet (element in line), whole line, * and entire cache (ie. all lines) level. The ICACHE only flushes are * ROSS HyperSparc specific and are in ross.h */ /* Flushes which clear out both the on-chip and external caches */ extern inline void flush_ei_page(unsigned int addr) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_FLUSH_PAGE) : "memory"); } extern inline void flush_ei_seg(unsigned int addr) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_FLUSH_SEG) : "memory"); } extern inline void flush_ei_region(unsigned int addr) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_FLUSH_REGION) : "memory"); } extern inline void flush_ei_ctx(unsigned int addr) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_FLUSH_CTX) : "memory"); } extern inline void flush_ei_user(unsigned int addr) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_FLUSH_USER) : "memory"); } #endif /* !(_SPARC_CACHE_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/checksum.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/checksum.h?rev=1.1&content-type=text/x-cvsweb-markup Index: checksum.h =================================================================== /* $Id: checksum.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */ #ifndef __SPARC_CHECKSUM_H #define __SPARC_CHECKSUM_H /* checksum.h: IP/UDP/TCP checksum routines on the Sparc. * * Copyright(C) 1995 Linus Torvalds * Copyright(C) 1995 Miguel de Icaza * Copyright(C) 1996 David S. Miller * * derived from: * Alpha checksum c-code * ix86 inline assembly */ /* * computes the checksum of the TCP/UDP pseudo-header * returns a 16-bit checksum, already complemented */ extern inline unsigned short csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len, unsigned short proto, unsigned int sum) { __asm__ __volatile__(" addcc %0, %1, %0 addxcc %0, %4, %0 addxcc %0, %5, %0 addx %0, %%g0, %0 ! We need the carry from the addition of 16-bit ! significant addition, so we zap out the low bits ! in one half, zap out the high bits in another, ! shift them both up to the top 16-bits of a word ! and do the carry producing addition, finally ! shift the result back down to the low 16-bits. ! Actually, we can further optimize away two shifts ! because we know the low bits of the original ! value will be added to zero-only bits so cannot ! affect the addition result nor the final carry ! bit. sll %0, 16, %1 addcc %0, %1, %0 ! add and set carry, neat eh? srl %0, 16, %0 ! shift back down the result addx %0, %%g0, %0 ! get remaining carry bit xnor %%g0, %0, %0 ! negate, sparc is cool " : "=&r" (sum), "=&r" (saddr) : "0" (daddr), "1" (saddr), "r" (len+proto), "r" (sum)); return ((unsigned short) sum); } extern inline unsigned short from32to16(unsigned long x) { __asm__ __volatile__(" addcc %0, %1, %0 srl %0, 16, %0 addx %%g0, %0, %0 " : "=r" (x) : "r" (x << 16), "0" (x)); return x; } extern inline unsigned long do_csum(unsigned char * buff, int len) { int odd, count; unsigned long result = 0; if (len <= 0) goto out; odd = 1 & (unsigned long) buff; if (odd) { result = *buff; len--; buff++; } count = len >> 1; /* nr of 16-bit words.. */ if (count) { if (2 & (unsigned long) buff) { result += *(unsigned short *) buff; count--; len -= 2; buff += 2; } count >>= 1; /* nr of 32-bit words.. */ if (count) { unsigned long carry = 0; do { unsigned long w = *(unsigned long *) buff; count--; buff += 4; result += carry; result += w; carry = (w > result); } while (count); result += carry; result = (result & 0xffff) + (result >> 16); } if (len & 2) { result += *(unsigned short *) buff; buff += 2; } } if (len & 1) result += (*buff << 8); result = from32to16(result); if (odd) result = ((result >> 8) & 0xff) | ((result & 0xff) << 8); out: return result; } /* ihl is always 5 or greater, almost always is 5, iph is always word * aligned but can fail to be dword aligned very often. */ extern inline unsigned short ip_fast_csum(const unsigned char *iph, unsigned int ihl) { unsigned int sum; __asm__ __volatile__(" ld [%1], %0 sub %2, 4, %2 ld [%1 + 0x4], %%g1 ld [%1 + 0x8], %%g2 addcc %%g1, %0, %0 addxcc %%g2, %0, %0 ld [%1 + 0xc], %%g1 ld [%1 + 0x10], %%g2 addxcc %%g1, %0, %0 addxcc %0, %%g0, %0 1: addcc %%g2, %0, %0 add %1, 0x4, %1 addxcc %0, %%g0, %0 subcc %2, 0x1, %2 bne,a 1b ld [%1 + 0x10], %%g2 sll %0, 16, %2 addcc %0, %2, %2 srl %2, 16, %0 addx %0, %%g0, %2 xnor %%g0, %2, %0 2: " : "=&r" (sum), "=&r" (iph), "=&r" (ihl) : "1" (iph), "2" (ihl) : "g1", "g2"); return sum; } /* * computes the checksum of a memory block at buff, length len, * and adds in "sum" (32-bit) * * returns a 32-bit number suitable for feeding into itself * or csum_tcpudp_magic * * this function must be called with even lengths, except * for the last fragment, which may be odd * * it's best to have buff aligned on a 32-bit boundary */ extern inline unsigned int csum_partial(unsigned char * buff, int len, unsigned int sum) { __asm__ __volatile__(" mov 0, %%g5 ! g5 = result cmp %1, 0 bgu,a 1f andcc %0, 1, %%g7 ! g7 = odd b,a 9f 1: be,a 1f srl %1, 1, %%g6 ! g6 = count = (len >> 1) sub %1, 1, %1 ! if(odd) { result = *buff; ldub [%0], %%g5 ! len--; add %0, 1, %0 ! buff++ } srl %1, 1, %%g6 1: cmp %%g6, 0 ! if (count) { be,a 8f andcc %1, 1, %%g0 andcc %0, 2, %%g0 ! if (2 & buff) { be,a 1f srl %%g6, 1, %%g6 sub %1, 2, %1 ! result += *(unsigned short *) buff; lduh [%0], %%g1 ! count--; sub %%g6, 1, %%g6 ! len -= 2; add %%g1, %%g5, %%g5! buff += 2; add %0, 2, %0 ! } srl %%g6, 1, %%g6 1: cmp %%g6, 0 ! if (count) { be,a 2f andcc %1, 2, %%g0 ld [%0], %%g1 ! csum aligned 32bit words 1: add %0, 4, %0 addcc %%g1, %%g5, %%g5 addx %%g5, %%g0, %%g5 subcc %%g6, 1, %%g6 bne,a 1b ld [%0], %%g1 sethi %%hi(0xffff), %%g3 srl %%g5, 16, %%g2 or %%g3, %%lo(0xffff), %%g3 and %%g5, %%g3, %%g5 add %%g2, %%g5, %%g5! } andcc %1, 2, %%g0 2: be,a 8f ! if (len & 2) { andcc %1, 1, %%g0 lduh [%0], %%g1 ! result += *(unsigned short *) buff; add %%g5, %%g1, %%g5! buff += 2; add %0, 2, %0 ! } andcc %1, 1, %%g0 8: be,a 1f ! if (len & 1) { sll %%g5, 16, %%g1 ldub [%0], %%g1 sll %%g1, 8, %%g1 ! result += (*buff << 8); add %%g5, %%g1, %%g5! } sll %%g5, 16, %%g1 1: addcc %%g1, %%g5, %%g5! result = from32to16(result); srl %%g5, 16, %%g1 addx %%g0, %%g1, %%g5 orcc %%g7, %%g0, %%g0! if(odd) { be 9f srl %%g5, 8, %%g1 and %%g5, 0xff, %%g2! result = ((result >> 8) & 0xff) | and %%g1, 0xff, %%g1! ((result & 0xff) << 8); sll %%g2, 8, %%g2 or %%g2, %%g1, %%g5! } 9: addcc %2, %%g5, %2 ! add result and sum with carry addx %%g0, %2, %2 " : "=&r" (buff), "=&r" (len), "=&r" (sum) : "0" (buff), "1" (len), "2" (sum) : "g1", "g2", "g3", "g5", "g6", "g7"); return sum; } /* * the same as csum_partial, but copies from fs:src while it * checksums * * here even more important to align src and dst on a 32-bit (or even * better 64-bit) boundary */ extern inline unsigned int csum_partial_copy(char *src, char *dst, int len, int sum) { /* * The whole idea is to do the copy and the checksum at * the same time, but we do it the easy way now. * * At least csum on the source, not destination, for cache * reasons.. */ sum = csum_partial(src, len, sum); memcpy(dst, src, len); return sum; } /* * this routine is used for miscellaneous IP-like checksums, mainly * in icmp.c */ extern inline unsigned short ip_compute_csum(unsigned char * buff, int len) { return ~from32to16(do_csum(buff,len)); } #define csum_partial_copy_fromuser(s, d, l, w) \ csum_partial_copy((char *) (s), (d), (l), (w)) /* * Fold a partial checksum without adding pseudo headers */ extern inline unsigned int csum_fold(unsigned int sum) { __asm__ __volatile__(" addcc %0, %1, %0 srl %0, 16, %0 addx %%g0, %0, %0 xnor %%g0, %0, %0 " : "=r" (sum) : "r" (sum << 16), "0" (sum)); return sum; } #endif /* !(__SPARC_CHECKSUM_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/clock.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/clock.h?rev=1.1&content-type=text/x-cvsweb-markup Index: clock.h =================================================================== /* $Id: clock.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * clock.h: Definitions for clock operations on the Sparc. * * Copyright (C) 1995 David S. Miller (davem@c...) */ #ifndef _SPARC_CLOCK_H #define _SPARC_CLOCK_H /* Foo for now. */ #endif /* !(_SPARC_CLOCK_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/contregs.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/contregs.h?rev=1.1&content-type=text/x-cvsweb-markup Index: contregs.h =================================================================== /* $Id: contregs.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */ #ifndef _SPARC_CONTREGS_H #define _SPARC_CONTREGS_H /* contregs.h: Addresses of registers in the ASI_CONTROL alternate address * space. These are for the mmu's context register, etc. * * Copyright (C) 1995 David S. Miller (davem@c...) */ /* 4=sun4 (as in sun4 sysmaint student book), c=sun4c (according to davem) */ #define AC_IDPROM 0x00000000 /* 4 ID PROM, R/O, byte, 32 bytes */ #define AC_CONTEXT 0x30000000 /* 4c current mmu-context */ #define AC_SENABLE 0x40000000 /* 4c system dvma/cache/reset enable reg */ #define AC_UDVMA_ENB 0x50000000 /* 4 Not used on Sun boards, byte */ #define AC_BUS_ERROR 0x60000000 /* 4 Cleared on read, byte. */ #define AC_SYNC_ERR 0x60000000 /* c fault type */ #define AC_SYNC_VA 0x60000004 /* c fault virtual address */ #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */ #define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */ #define AC_LEDS 0x70000000 /* 4 Zero turns on LEDs, byte */ #define AC_CACHETAGS 0x80000000 /* 4c direct access to the VAC tags */ #define AC_CACHEDDATA 0x90000000 /* c direct access to the VAC data */ #define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */ #define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */ #define AC_BOOT_SCC 0xF0000000 /* 4 bypass to access Zilog 8530. byte. */ /* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */ #define AC_M_PCR 0x0000 /* shv Processor Control Reg */ #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */ #define AC_M_CXR 0x0200 /* shv Context Register */ #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */ #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */ #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */ #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */ #define AC_M_RESET 0x0700 /* hv Reset Reg */ #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */ #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */ #define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */ #define AC_M_DAPTP 0x1200 /* hv Data Access PTP */ #define AC_M_ITR 0x1300 /* hv Index Tag Register */ #define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */ #define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */ #define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */ #define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */ #define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */ #define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */ #endif /* _SPARC_CONTREGS_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/cprefix.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/cprefix.h?rev=1.1&content-type=text/x-cvsweb-markup Index: cprefix.h =================================================================== /* cprefix.h: This file is included by assembly source which needs * to know what the c-label prefixes are. The newer versions * of cpp that come with gcc predefine such things to help * us out. The reason this stuff is needed is to make * solaris compiles of the kernel work. * * Copyright (C) 1995 David S. Miller (davem@c...) */ #ifndef __SPARC_CPREFIX_H #define __SPARC_CPREFIX_H #ifndef __svr4__ #define C_LABEL_PREFIX _ #else #define C_LABEL_PREFIX #endif #define CONCAT(a, b) CONCAT2(a, b) #define CONCAT2(a, b) a##b #define C_LABEL(name) CONCAT(C_LABEL_PREFIX, name) #endif /* !(__SPARC_CPREFIX_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/cypress.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/cypress.h?rev=1.1&content-type=text/x-cvsweb-markup Index: cypress.h =================================================================== /* $Id: cypress.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * cypress.h: Cypress module specific definitions and defines. * * Copyright (C) 1995 David S. Miller (davem@c...) */ #ifndef _SPARC_CYPRESS_H #define _SPARC_CYPRESS_H /* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */ /* The MMU control register fields on the Sparc Cypress 604/605 MMU's. * * --------------------------------------------------------------- * |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME| * --------------------------------------------------------------- * 31 24 23-22 21-20 19 18-15 14 13 12 11 10 9 8 7-2 1 0 * * MCA: MultiChip Access -- Used for configuration of multiple * CY7C604/605 cache units. * MCM: MultiChip Mask -- Again, for multiple cache unit config. * MV: MultiChip Valid -- Indicates MCM and MCA have valid settings. * MID: ModuleID -- Unique processor ID for MBus transactions. (605 only) * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode * C: Cacheable -- Indicates whether accesses are cacheable while * the MMU is off. 0=no 1=yes * MR: MemoryReflection -- Indicates whether the bus attached to the * MBus supports memory reflection. 0=no 1=yes (605 only) * CM: CacheMode -- Indicates whether the cache is operating in write * through or copy-back mode. 0=write-through 1=copy-back * CL: CacheLock -- Indicates if the entire cache is locked or not. * 0=not-locked 1=locked (604 only) * CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes * NF: NoFault -- Do faults generate traps? 0=yes 1=no * ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes */ #define CYPRESS_MCA 0x00c00000 #define CYPRESS_MCM 0x00300000 #define CYPRESS_MVALID 0x00080000 #define CYPRESS_MIDMASK 0x00078000 /* Only on 605 */ #define CYPRESS_BMODE 0x00004000 #define CYPRESS_ACENABLE 0x00002000 #define CYPRESS_MRFLCT 0x00000800 /* Only on 605 */ #define CYPRESS_CMODE 0x00000400 #define CYPRESS_CLOCK 0x00000200 /* Only on 604 */ #define CYPRESS_CENABLE 0x00000100 #define CYPRESS_NFAULT 0x00000002 #define CYPRESS_MENABLE 0x00000001 extern inline void cypress_flush_page(unsigned long page) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (page), "i" (ASI_M_FLUSH_PAGE)); } extern inline void cypress_flush_segment(unsigned long addr) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_FLUSH_SEG)); } extern inline void cypress_flush_region(unsigned long addr) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_FLUSH_REGION)); } extern inline void cypress_flush_context(void) { __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : : "i" (ASI_M_FLUSH_CTX)); } /* XXX Displacement flushes for buggy chips and initial testing * XXX go here. */ #endif /* !(_SPARC_CYPRESS_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/delay.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/delay.h?rev=1.1&content-type=text/x-cvsweb-markup Index: delay.h =================================================================== /* $Id: delay.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * delay.h: Linux delay routines on the Sparc. * * Copyright (C) 1994 David S. Miller (davem@c...). */ #ifndef __SPARC_DELAY_H #define __SPARC_DELAY_H extern unsigned long loops_per_sec; extern __inline__ void __delay(unsigned long loops) { __asm__ __volatile__("cmp %0, 0\n\t" "1: bne 1b\n\t" "subcc %0, 1, %0\n" : "=&r" (loops) : "0" (loops)); } /* This is too messy with inline asm on the Sparc. */ extern void udelay(unsigned long usecs); /* calibrate_delay() wants this... */ #define muldiv(a, b, c) (((a)*(b))/(c)) #endif /* defined(__SPARC_DELAY_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/dma.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/dma.h?rev=1.1&content-type=text/x-cvsweb-markup Index: dma.h =================================================================== /* $Id: dma.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * include/asm-sparc/dma.h * * Copyright 1995 (C) David S. Miller (davem@c...) */ #ifndef _ASM_SPARC_DMA_H #define _ASM_SPARC_DMA_H #include <linux/kernel.h> #include <asm/vac-ops.h> /* for invalidate's, etc. */ #include <asm/sbus.h> #include <asm/delay.h> #include <asm/oplib.h> /* These are irrelevant for Sparc DMA, but we leave it in so that * things can compile. */ #define MAX_DMA_CHANNELS 8 #define MAX_DMA_ADDRESS (~0UL) #define DMA_MODE_READ 1 #define DMA_MODE_WRITE 2 /* Useful constants */ #define SIZE_16MB (16*1024*1024) #define SIZE_64K (64*1024) /* Structure to describe the current status of DMA registers on the Sparc */ struct sparc_dma_registers { volatile unsigned long cond_reg; /* DMA condition register */ volatile char * st_addr; /* Start address of this transfer */ volatile unsigned long cnt; /* How many bytes to transfer */ volatile unsigned long dma_test; /* DMA test register */ }; /* DVMA chip revisions */ enum dvma_rev { dvmarev0, dvmaesc1, dvmarev1, dvmarev2, dvmarev3, dvmarevplus }; #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1) /* Linux DMA information structure, filled during probe. */ struct Linux_SBus_DMA { struct Linux_SBus_DMA *next; struct linux_sbus_device *SBus_dev; struct sparc_dma_registers *regs; /* Status, misc info */ int node; /* Prom node for this DMA device */ int running; /* Are we doing DMA now? */ int allocated; /* Are we "owned" by anyone yet? */ /* Transfer information. */ unsigned long addr; /* Start address of current transfer */ int nbytes; /* Size of current transfer */ int realbytes; /* For splitting up large transfers, etc. */ /* DMA revision */ enum dvma_rev revision; }; extern struct Linux_SBus_DMA *dma_chain; /* Broken hardware... */ #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1) #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1) /* Main routines in dma.c */ extern void dump_dma_regs(struct sparc_dma_registers *); extern unsigned long dvma_init(struct linux_sbus *, unsigned long); /* Fields in the cond_reg register */ /* First, the version identification bits */ #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */ #define DMA_VERS0 0x00000000 /* Sunray DMA version */ #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */ #define DMA_VERS1 0x80000000 /* DMA rev 1 */ #define DMA_VERS2 0xa0000000 /* DMA rev 2 */ #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */ #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */ #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */ #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */ #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */ #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */ #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */ #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ #define DMA_ST_WRITE 0x00000100 /* write from device to memory */ #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */ #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */ #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */ #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */ #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */ #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */ #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */ #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */ #define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */ #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */ #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */ #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */ #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */ #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */ #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */ #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */ #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */ #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */ #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */ /* Values describing the burst-size property from the PROM */ #define DMA_BURST1 0x01 #define DMA_BURST2 0x02 #define DMA_BURST4 0x04 #define DMA_BURST8 0x08 #define DMA_BURST16 0x10 #define DMA_BURST32 0x20 #define DMA_BURST64 0x40 #define DMA_BURSTBITS 0x7f /* Determine highest possible final transfer address given a base */ #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL)) /* Yes, I hack a lot of elisp in my spare time... */ #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR)) #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & DMA_HNDL_INTR)) #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE)) #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE))) #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB))) #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB))) #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV)) #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr)) #define DMA_BEGINDMA_W(regs) \ ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB)))) #define DMA_BEGINDMA_R(regs) \ ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE))))) /* For certain DMA chips, we need to disable ints upon irq entry * and turn them back on when we are done. So in any ESP interrupt * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT * when leaving the handler. You have been warned... */ #define DMA_IRQ_ENTRY(dma, dregs) do { \ if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \ } while (0) #define DMA_IRQ_EXIT(dma, dregs) do { \ if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \ } while(0) /* Pause until counter runs out or BIT isn't set in the DMA condition * register. */ extern inline void sparc_dma_pause(struct sparc_dma_registers *regs, unsigned long bit) { int ctr = 50000; /* Let's find some bugs ;) */ /* Busy wait until the bit is not set any more */ while((regs->cond_reg&bit) && (ctr>0)) { ctr--; __delay(5); } /* Check for bogus outcome. */ if(!ctr) panic("DMA timeout"); } /* Reset the friggin' thing... */ #define DMA_RESET(dma) do { \ struct sparc_dma_registers *regs = dma->regs; \ /* Let the current FIFO drain itself */ \ sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \ /* Reset the logic */ \ regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \ __delay(400); /* let the bits set ;) */ \ regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \ sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \ /* Enable FAST transfers if available */ \ if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \ dma->running = 0; \ } while(0) #define for_each_dvma(dma) \ for((dma) = dma_chain; (dma); (dma) = (dma)->next) extern int get_dma_list(char *); extern int request_dma(unsigned int, const char *); extern void free_dma(unsigned int); #endif /* !(_ASM_SPARC_DMA_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/ecc.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/ecc.h?rev=1.1&content-type=text/x-cvsweb-markup Index: ecc.h =================================================================== /* $Id: ecc.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * ecc.h: Definitions and defines for the external cache/memory * controller on the sun4m. * * Copyright (C) 1995 David S. Miller (davem@c...) */ #ifndef _SPARC_ECC_H #define _SPARC_ECC_H /* These registers are accessed through the SRMMU passthrough ASI 0x20 */ #define ECC_ENABLE 0x00000000 /* ECC enable register */ #define ECC_FSTATUS 0x00000008 /* ECC fault status register */ #define ECC_FADDR 0x00000010 /* ECC fault address register */ #define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */ #define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */ #define ECC_DMESG 0x00001000 /* Diagnostic message passing area */ /* ECC MBus Arbiter Enable register: * * ---------------------------------------- * | |SBUS|MOD3|MOD2|MOD1|RSV| * ---------------------------------------- * 31 5 4 3 2 1 0 * * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on */ #define ECC_MBAE_SBUS 0x00000010 #define ECC_MBAE_MOD3 0x00000008 #define ECC_MBAE_MOD2 0x00000004 #define ECC_MBAE_MOD1 0x00000002 /* ECC Fault Control Register layout: * * ----------------------------- * | RESV | ECHECK | EINT | * ----------------------------- * 31 2 1 0 * * ECHECK: Enable ECC checking. 0=off 1=on * EINT: Enable Interrupts for correctable errors. 0=off 1=on */ #define ECC_FCR_CHECK 0x00000002 #define ECC_FCR_INTENAB 0x00000001 /* ECC Fault Address Register Zero layout: * * ----------------------------------------------------- * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR | * ----------------------------------------------------- * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0 * * MID: ModuleID of the faulting processor. ie. who did it? * S: Supervisor/Privileged access? 0=no 1=yes * VA: Bits 19-12 of the virtual faulting address, these are the * superset bits in the virtual cache and can be used for * a flush operation if necessary. * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot * mode bit. * AT: Did this fault happen during an atomic instruction? 0=no * 1=yes. This means either an 'ldstub' or 'swap' instruction * was in progress (but not finished) when this fault happened. * This indicated whether the bus was locked when the fault * occurred. * C: Did the pte for this access indicate that it was cacheable? * 0=no 1=yes * SZ: The size of the transaction. * TYP: The transaction type. * PADDR: Bits 35-32 of the physical address for the fault. */ #define ECC_FADDR0_MIDMASK 0xf0000000 #define ECC_FADDR0_S 0x08000000 #define ECC_FADDR0_VADDR 0x003fc000 #define ECC_FADDR0_BMODE 0x00002000 #define ECC_FADDR0_ATOMIC 0x00001000 #define ECC_FADDR0_CACHE 0x00000800 #define ECC_FADDR0_SIZE 0x00000700 #define ECC_FADDR0_TYPE 0x000000f0 #define ECC_FADDR0_PADDR 0x0000000f /* ECC Fault Address Register One layout: * * ------------------------------------- * | Physical Address 31-0 | * ------------------------------------- * 31 0 * * You get the upper 4 bits of the physical address from the * PADDR field in ECC Fault Address Zero register. */ /* ECC Fault Status Register layout: * * ---------------------------------------------- * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C| * ---------------------------------------------- * 31-18 17 16 15-8 7-4 3 2 1 0 * * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only) * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes) * SYNDROME: Controller is mentally unstable. * DWORD: * UNC: Uncorrectable error. 0=no 1=yes * TIMEO: Timeout occurred. 0=no 1=yes * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only) * C: Correctable error? 0=no 1=yes */ #define ECC_FSR_C2ERR 0x00020000 #define ECC_FSR_MULT 0x00010000 #define ECC_FSR_SYND 0x0000ff00 #define ECC_FSR_DWORD 0x000000f0 #define ECC_FSR_UNC 0x00000008 #define ECC_FSR_TIMEO 0x00000004 #define ECC_FSR_BADSLOT 0x00000002 #define ECC_FSR_C 0x00000001 #endif /* !(_SPARC_ECC_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/eeprom.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/eeprom.h?rev=1.1&content-type=text/x-cvsweb-markup Index: eeprom.h =================================================================== /* $Id: eeprom.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * eeprom.h: Definitions for the Sun eeprom. * * Copyright (C) 1995 David S. Miller (davem@c...) */ /* The EEPROM and the Mostek Mk48t02 use the same IO address space * for their registers/data areas. The IDPROM lives here too. */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/elf.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/elf.h?rev=1.1&content-type=text/x-cvsweb-markup Index: elf.h =================================================================== /* $Id: elf.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */ #ifndef __ASMSPARC_ELF_H #define __ASMSPARC_ELF_H /* * ELF register definitions.. */ #include <asm/ptrace.h> typedef unsigned long elf_greg_t; #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef unsigned long elf_fpregset_t; /* * This is used to ensure we don't load something for the wrong architecture. */ #define elf_check_arch(x) ((x) == EM_SPARC) /* * These are used to set parameters in the core dumps. */ #define ELF_ARCH EM_SPARC #define ELF_CLASS ELFCLASS32 #define ELF_DATA ELFDATA2MSB; #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/errno.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/errno.h?rev=1.1&content-type=text/x-cvsweb-markup Index: errno.h =================================================================== /* $Id: errno.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */ #ifndef _SPARC_ERRNO_H #define _SPARC_ERRNO_H /* These match the SunOS error numbering scheme. */ #define EPERM 1 /* Operation not permitted */ #define ENOENT 2 /* No such file or directory */ #define ESRCH 3 /* No such process */ #define EINTR 4 /* Interrupted system call */ #define EIO 5 /* I/O error */ #define ENXIO 6 /* No such device or address */ #define E2BIG 7 /* Arg list too long */ #define ENOEXEC 8 /* Exec format error */ #define EBADF 9 /* Bad file number */ #define ECHILD 10 /* No child processes */ #define EAGAIN 11 /* Try again */ #define ENOMEM 12 /* Out of memory */ #define EACCES 13 /* Permission denied */ #define EFAULT 14 /* Bad address */ #define ENOTBLK 15 /* Block device required */ #define EBUSY 16 /* Device or resource busy */ #define EEXIST 17 /* File exists */ #define EXDEV 18 /* Cross-device link */ #define ENODEV 19 /* No such device */ #define ENOTDIR 20 /* Not a directory */ #define EISDIR 21 /* Is a directory */ #define EINVAL 22 /* Invalid argument */ #define ENFILE 23 /* File table overflow */ #define EMFILE 24 /* Too many open files */ #define ENOTTY 25 /* Not a typewriter */ #define ETXTBSY 26 /* Text file busy */ #define EFBIG 27 /* File too large */ #define ENOSPC 28 /* No space left on device */ #define ESPIPE 29 /* Illegal seek */ #define EROFS 30 /* Read-only file system */ #define EMLINK 31 /* Too many links */ #define EPIPE 32 /* Broken pipe */ #define EDOM 33 /* Math argument out of domain of func */ #define ERANGE 34 /* Math result not representable */ #define EWOULDBLOCK 35 /* Operation would block */ #define EINPROGRESS 36 /* Operation now in progress */ #define EALREADY 37 /* Operation already in progress */ #define ENOTSOCK 38 /* Socket operation on non-socket */ #define EDESTADDRREQ 39 /* Destination address required */ #define EMSGSIZE 40 /* Message too long */ #define EPROTOTYPE 41 /* Protocol wrong type for socket */ #define ENOPROTOOPT 42 /* Protocol not available */ #define EPROTONOSUPPORT 43 /* Protocol not supported */ #define ESOCKTNOSUPPORT 44 /* Socket type not supported */ #define EOPNOTSUPP 45 /* Op not supported on transport endpoint */ #define EPFNOSUPPORT 46 /* Protocol family not supported */ #define EAFNOSUPPORT 47 /* Address family not supported by protocol */ #define EADDRINUSE 48 /* Address already in use */ #define EADDRNOTAVAIL 49 /* Cannot assign requested address */ #define ENETDOWN 50 /* Network is down */ #define ENETUNREACH 51 /* Network is unreachable */ #define ENETRESET 52 /* Net dropped connection because of reset */ #define ECONNABORTED 53 /* Software caused connection abort */ #define ECONNRESET 54 /* Connection reset by peer */ #define ENOBUFS 55 /* No buffer space available */ #define EISCONN 56 /* Transport endpoint is already connected */ #define ENOTCONN 57 /* Transport endpoint is not connected */ #define ESHUTDOWN 58 /* No send after transport endpoint shutdown */ #define ETOOMANYREFS 59 /* Too many references: cannot splice */ #define ETIMEDOUT 60 /* Connection timed out */ #define ECONNREFUSED 61 /* Connection refused */ #define ELOOP 62 /* Too many symbolic links encountered */ #define ENAMETOOLONG 63 /* File name too long */ #define EHOSTDOWN 64 /* Host is down */ #define EHOSTUNREACH 65 /* No route to host */ #define ENOTEMPTY 66 /* Directory not empty */ #define EPROCLIM 67 /* SUNOS: Too many processes */ #define EUSERS 68 /* Too many users */ #define EDQUOT 69 /* Quota exceeded */ #define ESTALE 70 /* Stale NFS file handle */ #define EREMOTE 71 /* Object is remote */ #define ENOSTR 72 /* Device not a stream */ #define ETIME 73 /* Timer expired */ #define ENOSR 74 /* Out of streams resources */ #define ENOMSG 75 /* No message of desired type */ #define EBADMSG 76 /* Not a data message */ #define EIDRM 77 /* Identifier removed */ #define EDEADLK 78 /* Resource deadlock would occur */ #define ENOLCK 79 /* No record locks available */ #define ENONET 80 /* Machine is not on the network */ #define ERREMOTE 81 /* SunOS: Too many lvls of remote in path */ #define ENOLINK 82 /* Link has been severed */ #define EADV 83 /* Advertise error */ #define ESRMNT 84 /* Srmount error */ #define ECOMM 85 /* Communication error on send */ #define EPROTO 86 /* Protocol error */ #define EMULTIHOP 87 /* Multihop attempted */ #define EDOTDOT 88 /* RFS specific error */ #define EREMCHG 89 /* Remote address changed */ #define ENOSYS 90 /* Function not implemented */ /* The rest have no SunOS equivalent. */ #define ESTRPIPE 91 /* Streams pipe error */ #define EOVERFLOW 92 /* Value too large for defined data type */ #define EBADFD 93 /* File descriptor in bad state */ #define ECHRNG 94 /* Channel number out of range */ #define EL2NSYNC 95 /* Level 2 not synchronized */ #define EL3HLT 96 /* Level 3 halted */ #define EL3RST 97 /* Level 3 reset */ #define ELNRNG 98 /* Link number out of range */ #define EUNATCH 99 /* Protocol driver not attached */ #define ENOCSI 100 /* No CSI structure available */ #define EL2HLT 101 /* Level 2 halted */ #define EBADE 102 /* Invalid exchange */ #define EBADR 103 /* Invalid request descriptor */ #define EXFULL 104 /* Exchange full */ #define ENOANO 105 /* No anode */ #define EBADRQC 106 /* Invalid request code */ #define EBADSLT 107 /* Invalid slot */ #define EDEADLOCK 108 /* File locking deadlock error */ #define EBFONT 109 /* Bad font file format */ #define ELIBEXEC 110 /* Cannot exec a shared library directly */ #define ENODATA 111 /* No data available */ #define ELIBBAD 112 /* Accessing a corrupted shared library */ #define ENOPKG 113 /* Package not installed */ #define ELIBACC 114 /* Can not access a needed shared library */ #define ENOTUNIQ 115 /* Name not unique on network */ #define ERESTART 116 /* Interrupted syscall should be restarted */ #define EUCLEAN 117 /* Structure needs cleaning */ #define ENOTNAM 118 /* Not a XENIX named type file */ #define ENAVAIL 119 /* No XENIX semaphores available */ #define EISNAM 120 /* Is a named type file */ #define EREMOTEIO 121 /* Remote I/O error */ #define EILSEQ 122 /* Illegal byte sequence */ #define ELIBMAX 123 /* Atmpt to link in too many shared libs */ #define ELIBSCN 124 /* .lib section in a.out corrupted */ #define ENOMEDIUM 125 /* No medium found */ #define EMEDIUMTYPE 126 /* Wrong medium type */ #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/fbio.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/fbio.h?rev=1.1&content-type=text/x-cvsweb-markup Index: fbio.h =================================================================== #ifndef __LINUX_FBIO_H #define __LINUX_FBIO_H /* Constants used for fbio SunOS compatibility -miguel */ /* Frame buffer types */ #define FBTYPE_NOTYPE -1 #define FBTYPE_SUN1BW 0 /* mono */ #define FBTYPE_SUN1COLOR 1 #define FBTYPE_SUN2BW 2 #define FBTYPE_SUN2COLOR 3 #define FBTYPE_SUN2GP 4 #define FBTYPE_SUN5COLOR 5 #define FBTYPE_SUN3COLOR 6 #define FBTYPE_MEMCOLOR 7 #define FBTYPE_SUN4COLOR 8 #define FBTYPE_NOTSUN1 9 #define FBTYPE_NOTSUN2 10 #define FBTYPE_NOTSUN3 11 #define FBTYPE_SUNFAST_COLOR 12 /* cg6 */ #define FBTYPE_SUNROP_COLOR 13 #define FBTYPE_SUNFB_VIDEO 14 #define FBTYPE_SUNGIFB 15 #define FBTYPE_SUNGPLAS 16 #define FBTYPE_SUNGP3 17 #define FBTYPE_SUNGT 18 #define FBTYPE_SUNLEO 19 /* zx Leo card */ #define FBTYPE_MDICOLOR 20 /* cg14 */ #define FBTYPE_LASTPLUSONE 21 /* fbio ioctls */ /* Returned by FBIOGTYPE */ struct fbtype { int fb_type; /* fb type, see above */ int fb_height; /* pixels */ int fb_width; /* pixels */ int fb_depth; int fb_cmsize; /* color map entries */ int fb_size; /* fb size in bytes */ }; #define FBIOGTYPE _IOR('F', 0, struct fbtype) /* Used by FBIOPUTCMAP */ struct fbcmap { int index; /* first element (0 origin) */ int count; unsigned char *red; unsigned char *green; unsigned char *blue; }; #define FBIOPUTCMAP _IOW('F', 3, struct fbcmap) /* # of device specific values */ #define FB_ATTR_NDEVSPECIFIC 8 /* # of possible emulations */ #define FB_ATTR_NEMUTYPES 4 struct fbsattr { int flags; int emu_type; /* -1 if none */ int dev_specific[FB_ATTR_NDEVSPECIFIC]; }; struct fbgattr { int real_type; /* real frame buffer type */ int owner; /* unknown */ struct fbtype fbtype; /* real frame buffer fbtype */ struct fbsattr sattr; int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */ }; #define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */ #define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */ #define FBIOSVIDEO _IOW('F', 7, int) #define FBIOGVIDEO _IOR('F', 8, int) /* Cursor position */ struct fbcurpos { #ifdef __KERNEL__ short fbx, fby; #else short x, y; #endif }; /* Cursor operations */ #define FB_CUR_SETCUR 0x01 /* Enable/disable cursor display */ #define FB_CUR_SETPOS 0x02 /* set cursor position */ #define FB_CUR_SETHOT 0x04 /* set cursor hotspot */ #define FB_CUR_SETCMAP 0x08 /* set color map for the cursor */ #define FB_CUR_SETSHAPE 0x10 /* set shape */ #define FB_CUR_SETALL 0x1F /* all of the above */ struct fbcursor { short set; /* what to set, choose from the list above */ short enable; /* cursor on/off */ struct fbcurpos pos; /* cursor position */ struct fbcurpos hot; /* cursor hot spot */ struct fbcmap cmap; /* color map info */ struct fbcurpos size; /* cursor bit map size */ char *image; /* cursor image bits */ char *mask; /* cursor mask bits */ }; /* set/get cursor attributes/shape */ #define FBIOSCURSOR _IOW('F', 24, struct fbcursor) #define FBIOGCURSOR _IOWR('F', 25, struct fbcursor) /* set/get cursor position */ #define FBIOSCURPOS _IOW('F', 26, struct fbcurpos) #define FBIOGCURPOS _IOW('F', 27, struct fbcurpos) /* get max cursor size */ #define FBIOGCURMAX _IOR('F', 28, struct fbcurpos) #ifdef __KERNEL__ /* Addresses on the fd of a cgsix that are mappable */ #define CG6_FBC 0x70000000 #define CG6_TEC 0x70001000 #define CG6_BTREGS 0x70002000 #define CG6_FHC 0x70004000 #define CG6_THC 0x70005000 #define CG6_ROM 0x70006000 #define CG6_RAM 0x70016000 #define CG6_DHC 0x80000000 #define CG3_MMAP_OFFSET 0x4000000 #endif /* KERNEL */ #endif /* __LINUX_FBIO_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/fcntl.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/fcntl.h?rev=1.1&content-type=text/x-cvsweb-markup Index: fcntl.h =================================================================== /* $Id: fcntl.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */ #ifndef _SPARC_FCNTL_H #define _SPARC_FCNTL_H /* open/fcntl - O_SYNC is only implemented on blocks devices and on files located on an ext2 file system */ #define O_RDONLY 0x0000 #define O_WRONLY 0x0001 #define O_RDWR 0x0002 #define O_ACCMODE 0x0003 #define O_NDELAY 0x0004 #define O_APPEND 0x0008 #define FASYNC 0x0040 /* fcntl, for BSD compatibility */ #define O_CREAT 0x0200 /* not fcntl */ #define O_TRUNC 0x0400 /* not fcntl */ #define O_EXCL 0x0800 /* not fcntl */ #define O_SYNC 0x2000 #define O_NONBLOCK 0x4000 #define O_NOCTTY 0x8000 /* not fcntl */ #define F_DUPFD 0 /* dup */ #define F_GETFD 1 /* get f_flags */ #define F_SETFD 2 /* set f_flags */ #define F_GETFL 3 /* more flags (cloexec) */ #define F_SETFL 4 #define F_GETOWN 5 /* for sockets. */ #define F_SETOWN 6 /* for sockets. */ #define F_GETLK 7 #define F_SETLK 8 #define F_SETLKW 9 /* for F_[GET|SET]FL */ #define FD_CLOEXEC 1 /* actually anything with low bit set goes */ /* for posix fcntl() and lockf() */ #define F_RDLCK 1 #define F_WRLCK 2 #define F_UNLCK 3 /* for old implementation of bsd flock () */ #define F_EXLCK 4 /* or 3 */ #define F_SHLCK 8 /* or 4 */ /* operations for bsd flock(), also used by the kernel implementation */ #define LOCK_SH 1 /* shared lock */ #define LOCK_EX 2 /* exclusive lock */ #define LOCK_NB 4 /* or'd with one of the above to prevent blocking */ #define LOCK_UN 8 /* remove lock */ struct flock { short l_type; short l_whence; off_t l_start; off_t l_len; pid_t l_pid; short __unused; }; #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/floppy.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/floppy.h?rev=1.1&content-type=text/x-cvsweb-markup Index: floppy.h =================================================================== /* asm-sparc/floppy.h: Sparc specific parts of the Floppy driver. * * Copyright (C) 1995 David S. Miller (davem@c...) */ #ifndef __ASM_SPARC_FLOPPY_H #define __ASM_SPARC_FLOPPY_H #include <asm/page.h> #include <asm/pgtable.h> #include <asm/system.h> #include <asm/idprom.h> #include <asm/machines.h> #include <asm/oplib.h> #include <asm/auxio.h> #include <asm/irq.h> /* References: * 1) Netbsd Sun floppy driver. * 2) NCR 82077 controller manual * 3) Intel 82077 controller manual */ struct sun_flpy_controller { volatile unsigned char status_82072; /* Main Status reg. */ #define dcr_82072 status_82072 /* Digital Control reg. */ #define status1_82077 status_82072 /* Auxiliary Status reg. 1 */ volatile unsigned char data_82072; /* Data fifo. */ #define status2_82077 data_82072 /* Auxiliary Status reg. 2 */ volatile unsigned char dor_82077; /* Digital Output reg. */ volatile unsigned char tapectl_82077; /* What the? Tape control reg? */ volatile unsigned char status_82077; /* Main Status Register. */ #define drs_82077 status_82077 /* Digital Rate Select reg. */ volatile unsigned char data_82077; /* Data fifo. */ volatile unsigned char ___unused; volatile unsigned char dir_82077; /* Digital Input reg. */ #define dcr_82077 dir_82077 /* Config Control reg. */ }; /* You'll only ever find one controller on a SparcStation anyways. */ static struct sun_flpy_controller *sun_fdc = NULL; volatile unsigned char *fdc_status; struct sun_floppy_ops { unsigned char (*fd_inb)(int port); void (*fd_outb)(unsigned char value, int port); }; static struct sun_floppy_ops sun_fdops; #define fd_inb(port) sun_fdops.fd_inb(port) #define fd_outb(value,port) sun_fdops.fd_outb(value,port) #define fd_enable_dma() sun_fd_enable_dma() #define fd_disable_dma() sun_fd_disable_dma() #define fd_request_dma() (0) /* nothing... */ #define fd_free_dma() /* nothing... */ #define fd_clear_dma_ff() /* nothing... */ #define fd_set_dma_mode(mode) sun_fd_set_dma_mode(mode) #define fd_set_dma_addr(addr) sun_fd_set_dma_addr(addr) #define fd_set_dma_count(count) sun_fd_set_dma_count(count) #define fd_enable_irq() /* nothing... */ #define fd_disable_irq() /* nothing... */ #define fd_cacheflush(addr, size) /* nothing... */ #define fd_request_irq() sun_fd_request_irq() #define fd_free_irq() /* nothing... */ #if 0 /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */ #define fd_dma_mem_alloc(size) ((unsigned long) vmalloc(size)) #define fd_dma_mem_free(addr,size) (vfree((void *)(addr))) #endif #define FLOPPY_MOTOR_MASK 0x10 /* It's all the same... */ #define virt_to_bus(x) (x) #define bus_to_virt(x) (x) /* XXX This isn't really correct. XXX */ #define get_dma_residue(x) (0) #define FLOPPY0_TYPE 4 #define FLOPPY1_TYPE 0 /* Super paranoid... */ #undef HAVE_DISABLE_HLT /* Here is where we catch the floppy driver trying to initialize, * therefore this is where we call the PROM device tree probing * routine etc. on the Sparc. */ #define FDC1 sun_floppy_init() static int FDC2=-1; #define N_FDC 1 #define N_DRIVE 8 /* No 64k boundary crossing problems on the Sparc. */ #define CROSS_64KB(a,s) (0) /* Routines unique to each controller type on a Sun. */ static unsigned char sun_82072_fd_inb(int port) { switch(port & 7) { default: printk("floppy: Asked to read unknown port %d\n", port); panic("floppy: Port bolixed."); case 4: /* FD_STATUS */ return sun_fdc->status_82072 & ~STATUS_DMA; case 5: /* FD_DATA */ return sun_fdc->data_82072; case 7: /* FD_DIR */ return (*AUXREG & AUXIO_FLPY_DCHG)? 0x80: 0; }; panic("sun_82072_fd_inb: How did I get here?"); } static void sun_82072_fd_outb(unsigned char value, int port) { switch(port & 7) { default: printk("floppy: Asked to write to unknown port %d\n", port); panic("floppy: Port bolixed."); case 2: /* FD_DOR */ /* Oh geese, 82072 on the Sun has no DOR register, * the functionality is implemented via the AUXIO * I/O register. So we must emulate the behavior. * * ASSUMPTIONS: There will only ever be one floppy * drive attached to a Sun controller * and it will be at drive zero. */ { unsigned bits = 0; if (value & 0x10) bits |= AUXIO_FLPY_DSEL; if ((value & 0x80) == 0) bits |= AUXIO_FLPY_EJCT; set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT)); } break; case 5: /* FD_DATA */ sun_fdc->data_82072 = value; break; case 7: /* FD_DCR */ sun_fdc->dcr_82072 = value; break; case 4: /* FD_STATUS */ sun_fdc->status_82072 = value; break; }; return; } static unsigned char sun_82077_fd_inb(int port) { switch(port & 7) { default: printk("floppy: Asked to read unknown port %d\n", port); panic("floppy: Port bolixed."); case 4: /* FD_STATUS */ return sun_fdc->status_82077 & ~STATUS_DMA; case 5: /* FD_DATA */ return sun_fdc->data_82077; case 7: /* FD_DIR */ /* XXX: Is DCL on 0x80 in sun4m? */ return sun_fdc->dir_82077; }; panic("sun_82072_fd_inb: How did I get here?"); } static void sun_82077_fd_outb(unsigned char value, int port) { switch(port & 7) { default: printk("floppy: Asked to write to unknown port %d\n", port); panic("floppy: Port bolixed."); case 2: /* FD_DOR */ /* Happily, the 82077 has a real DOR register. */ sun_fdc->dor_82077 = value; break; case 5: /* FD_DATA */ sun_fdc->data_82077 = value; break; case 7: /* FD_DCR */ sun_fdc->dcr_82077 = value; break; case 4: /* FD_STATUS */ sun_fdc->status_82077 = value; break; }; return; } /* For pseudo-dma (Sun floppy drives have no real DMA available to * them so we must eat the data fifo bytes directly ourselves) we have * three state variables. doing_pdma tells our inline low-level * assembly floppy interrupt entry point whether it should sit and eat * bytes from the fifo or just transfer control up to the higher level * floppy interrupt c-code. I tried very hard but I could not get the * pseudo-dma to work in c-code without getting many overruns and * underruns. If non-zero, doing_pdma encodes the direction of * the transfer for debugging. 1=read 2=write */ char *pdma_vaddr; unsigned long pdma_size; volatile int doing_pdma = 0; /* This is software state */ char *pdma_base = 0; unsigned long pdma_areasize; /* Common routines to all controller types on the Sparc. */ static inline void virtual_dma_init(void) { /* nothing... */ } static inline void sun_fd_disable_dma(void) { doing_pdma = 0; if (pdma_base) { mmu_unlockarea(pdma_base, pdma_areasize); pdma_base = 0; } } static inline void sun_fd_set_dma_mode(int mode) { switch(mode) { case DMA_MODE_READ: doing_pdma = 1; break; case DMA_MODE_WRITE: doing_pdma = 2; break; default: printk("Unknown dma mode %d\n", mode); panic("floppy: Giving up..."); } } static inline void sun_fd_set_dma_addr(char *buffer) { pdma_vaddr = buffer; } static inline void sun_fd_set_dma_count(int length) { pdma_size = length; } static inline void sun_fd_enable_dma(void) { pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size); pdma_base = pdma_vaddr; pdma_areasize = pdma_size; } /* Our low-level entry point in arch/sparc/kernel/entry.S */ extern void floppy_hardint(int irq, void *unused, struct pt_regs *regs); static int sun_fd_request_irq(void) { static int once = 0; int error; if(!once) { once = 1; error = request_fast_irq(FLOPPY_IRQ, floppy_hardint, SA_INTERRUPT, "floppy"); return ((error == 0) ? 0 : -1); } else return 0; } static struct linux_prom_registers fd_regs[2]; static int sun_floppy_init(void) { char state[128]; int tnode, fd_node, num_regs; use_virtual_dma = 1; FLOPPY_IRQ = 11; /* Forget it if we aren't on a machine that could possibly * ever have a floppy drive. */ if((sparc_cpu_model != sun4c && sparc_cpu_model != sun4m) || ((idprom->id_machtype == (SM_SUN4C | SM_4C_SLC)) || (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC)))) { /* We certainly don't have a floppy controller. */ goto no_sun_fdc; } /* Well, try to find one. */ tnode = prom_getchild(prom_root_node); fd_node = prom_searchsiblings(tnode, "obio"); if(fd_node != 0) { tnode = prom_getchild(fd_node); fd_node = prom_searchsiblings(tnode, "SUNW,fdtwo"); } else { fd_node = prom_searchsiblings(tnode, "fd"); } if(fd_node == 0) { goto no_sun_fdc; } /* The sun4m lets us know if the controller is actually usable. */ if(sparc_cpu_model == sun4m) { prom_getproperty(fd_node, "status", state, sizeof(state)); if(!strcmp(state, "disabled")) { goto no_sun_fdc; } } num_regs = prom_getproperty(fd_node, "reg", (char *) fd_regs, sizeof(fd_regs)); num_regs = (num_regs / sizeof(fd_regs[0])); prom_apply_obio_ranges(fd_regs, num_regs); sun_fdc = (struct sun_flpy_controller *) sparc_alloc_io(fd_regs[0].phys_addr, 0x0, fd_regs[0].reg_size, "floppy", fd_regs[0].which_io, 0x0); /* Last minute sanity check... */ if(sun_fdc->status_82072 == 0xff) { sun_fdc = NULL; goto no_sun_fdc; } if(sparc_cpu_model == sun4c) { sun_fdops.fd_inb = sun_82072_fd_inb; sun_fdops.fd_outb = sun_82072_fd_outb; fdc_status = &sun_fdc->status_82072; /* printk("AUXIO @0x%p\n", auxio_register); */ /* P3 */ } else { sun_fdops.fd_inb = sun_82077_fd_inb; sun_fdops.fd_outb = sun_82077_fd_outb; fdc_status = &sun_fdc->status_82077; /* printk("DOR @0x%p\n", &sun_fdc->dor_82077); */ /* P3 */ } /* Success... */ return (int) sun_fdc; no_sun_fdc: return -1; } static int sparc_eject(void) { set_dor(0, ~0, 0x90); udelay(500); set_dor(0, ~0x90, 0); udelay(500); return 0; } #define fd_eject(drive) sparc_eject() #endif /* !(__ASM_SPARC_FLOPPY_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/head.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/head.h?rev=1.1&content-type=text/x-cvsweb-markup Index: head.h =================================================================== /* $Id: head.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */ #ifndef __SPARC_HEAD_H #define __SPARC_HEAD_H #define KERNBASE 0xf0000000 /* First address the kernel will eventually be */ #define LOAD_ADDR 0x4000 /* prom jumps to us here unless this is elf /boot */ #define SUN4C_SEGSZ (1 << 18) #define SRMMU_L1_KBASE_OFFSET ((KERNBASE>>24)<<2) /* Used in boot remapping. */ #define INTS_ENAB 0x01 /* entry.S uses this. */ #define NCPUS 4 /* Architectural limit of sun4m. */ #define SUN4_PROM_VECTOR 0xFFE81000 /* To safely die on a SUN4 */ #define SUN4_PRINTF 0x84 /* Offset into SUN4_PROM_VECTOR */ #define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */ #define NOP_INSN 0x01000000 /* Used to patch sparc_save_state */ /* Here are some trap goodies */ /* Generic trap entry. */ #define TRAP_ENTRY(type, label) \ rd %psr, %l0; b label; rd %wim, %l3; nop; /* Data/text faults. Defaults to sun4c version at boot time. */ #define SPARC_TFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 1, %l7; #define SPARC_DFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 0, %l7; #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b C_LABEL(srmmu_fault); mov 1, %l7; #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b C_LABEL(srmmu_fault); mov 0, %l7; /* This is for traps we should NEVER get. */ #define BAD_TRAP(num) \ rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3; /* Notice that for the system calls we pull a trick. We load up a * different pointer to the system call vector table in %l7, but call * the same generic system call low-level entry point. The trap table * entry sequences are also HyperSparc pipeline friendly ;-) */ /* Software trap for Linux system calls. */ #define LINUX_SYSCALL_TRAP \ sethi %hi(C_LABEL(sys_call_table)), %l7; \ or %l7, %lo(C_LABEL(sys_call_table)), %l7; \ b linux_sparc_syscall; \ rd %psr, %l0; /* Software trap for SunOS4.1.x system calls. */ #define SUNOS_SYSCALL_TRAP \ rd %psr, %l0; \ sethi %hi(C_LABEL(sunos_sys_table)), %l7; \ b linux_sparc_syscall; \ or %l7, %lo(C_LABEL(sunos_sys_table)), %l7; /* Software trap for Slowaris system calls. */ #define SOLARIS_SYSCALL_TRAP \ sethi %hi(C_LABEL(sys_call_table)), %l7; \ or %l7, %lo(C_LABEL(sys_call_table)), %l7; \ b solaris_syscall; \ rd %psr, %l0; /* Software trap for Sparc-netbsd system calls. */ #define NETBSD_SYSCALL_TRAP \ sethi %hi(C_LABEL(sys_call_table)), %l7; \ or %l7, %lo(C_LABEL(sys_call_table)), %l7; \ b bsd_syscall; \ rd %psr, %l0; /* The Get Condition Codes software trap for userland. */ #define GETCC_TRAP \ b getcc_trap_handler; mov %psr, %l0; nop; nop; /* The Set Condition Codes software trap for userland. */ #define SETCC_TRAP \ b setcc_trap_handler; mov %psr, %l0; nop; nop; /* This is for hard interrupts from level 1-14, 15 is non-maskable (nmi) and * gets handled with another macro. */ #define TRAP_ENTRY_INTERRUPT(int_level) \ mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3; /* NMI's (Non Maskable Interrupts) are special, you can't keep them * from coming in, and basically if you get one, the shows over. ;( * On the sun4c they are usually asynchronous memory errors, on the * the sun4m they could be either due to mem errors or a software * initiated interrupt from the prom/kern on an SMP box saying "I * command you to do CPU tricks, read your mailbox for more info." */ #define NMI_TRAP \ rd %wim, %l3; b linux_trap_nmi_sun4c; mov %psr, %l0; nop; /* Window overflows/underflows are special and we need to try to be as * efficient as possible here.... */ #define WINDOW_SPILL \ rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0; #define WINDOW_FILL \ rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0; #endif __SPARC_HEAD_H 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/idprom.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/idprom.h?rev=1.1&content-type=text/x-cvsweb-markup Index: idprom.h =================================================================== /* $Id: idprom.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ * idprom.h: Macros and defines for idprom routines * * Copyright (C) 1995 David S. Miller (davem@c...) */ #ifndef _SPARC_IDPROM_H #define _SPARC_IDPROM_H extern struct linux_romvec *romvec; /* Offset into the EEPROM where the id PROM is located on the 4c */ #define IDPROM_OFFSET 0x7d8 /* On sun4m; physical. */ /* MicroSPARC(-II) does not decode 31rd bit, but it works. */ #define IDPROM_OFFSET_M 0xfd8 struct idp_struct { unsigned char id_f_id; /* format identifier */ unsigned char id_machtype; /* Machine type */ unsigned char id_eaddr[6]; /* hardware ethernet address */ long id_domf; /* Date when this machine was manufactured */ unsigned int id_sernum:24; /* Unique serial number */ unsigned char id_cksum; /* XXX */ unsigned char dummy[16]; /* XXX */ }; extern struct idp_struct *idprom; #define IDPROM_SIZE (sizeof(struct idp_struct)) #endif /* !(_SPARC_IDPROM_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-sparc/io.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-sparc/io.h?rev=1.1&content-type=text/x-cvsweb-markup Index: io.h =================================================================== /* $Id: io.h,v 1.1 2005/12/20 11:32:11 jcastillo Exp $ */ #ifndef __SPARC_IO_H #define __SPARC_IO_H #include <linux/kernel.h> #include <asm/page.h> /* IO address mapping routines need this */ #include <asm/system.h> /* * Defines for io operations on the Sparc. Whether a memory access is going