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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Tue Dec 20 12:28:22 CET 2005
    Subject: [cvs-checkins] MODIFIED: or1k ...
    Top
    Date: 00/05/12 20:12:28

    Added: or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio
    a.out.h dma.h hardware.h io.h irq.h irqs.h mmu.h
    oldlatches.h processor.h serial.h shmparam.h
    system.h time.h uncompress.h
    Log:
    First Import of RC20x uClinux


    Revision Changes Path
    1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/a.out.h

    http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/a.out.h?rev=1.1&content-type=text/x-cvsweb-markup

    Index: a.out.h
    ===================================================================
    /*
    * linux/include/asm-arm/arch-a5k/a.out.h
    *
    * Copyright (C) 1996 Russell King
    */

    #ifndef __ASM_ARCH_A_OUT_H
    #define __ASM_ARCH_A_OUT_H

    #ifdef __KERNEL__
    //#define STACK_TOP (0x01a00000)
    //#define LIBRARY_START_TEXT (0x00c00000)
    #endif

    #endif




    1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/dma.h

    http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/dma.h?rev=1.1&content-type=text/x-cvsweb-markup

    Index: dma.h
    ===================================================================
    #ifndef __ASM_ARCH_DMA_H
    #define __ASM_ARCH_DMA_H

    /*
    * This is the maximum DMA address that can be DMAd to.
    */
    #define MAX_DMA_ADDRESS 0x03000000

    /*
    * DMA modes - we have two, IN and OUT
    */
    typedef enum {
    DMA_MODE_READ,
    DMA_MODE_WRITE
    } dmamode_t;

    #define MAX_DMA_CHANNELS 2
    #define DMA_VIRTUAL_FLOPPY 0
    #define DMA_VIRTUAL_SOUND 1

    #define DMA_FLOPPY DMA_VIRTUAL_FLOPPY

    #endif /* _ASM_ARCH_DMA_H */




    1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/hardware.h

    http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/hardware.h?rev=1.1&content-type=text/x-cvsweb-markup

    Index: hardware.h
    ===================================================================
    /*
    * linux/include/asm-arm/arch-trio/hardware.h
    *
    * Copyright (C) 1996 Russell King.
    *
    * This file contains the hardware definitions of the APLIO TRIO series machines.
    */

    #ifndef __ASM_ARCH_HARDWARE_H
    #define __ASM_ARCH_HARDWARE_H

    /*
    * What hardware must be present
    */
    #ifndef __ASSEMBLER__

    typedef unsigned long u_32;
    /* ARM asynchronous clock */
    #define ARM_CLK ((u_32)(24000000))
    /* ARM synchronous with OAK clock */
    #define A_O_CLK ((u_32)(20000000))

    #else

    #define ARM_CLK 24000000
    #define A_O_CLK 20000000

    #endif #ifndef __ASSEMBLER__ /* * RAM definitions */ #define MAPTOPHYS(a) ((unsigned long)a) #define KERNTOPHYS(a) ((unsigned long)(&a)) #define GET_MEMORY_END(p) ((p->u1.s.page_size) * (p->u1.s.nr_pages)) #define PARAMS_BASE 0x1000 //#define KERNEL_BASE (PAGE_OFFSET + 0x80000) #endif #define IO_BASE 0 #define PERIPH_BASE 0xff000000 #define OAKA_PRAM 0xfd000000 #define OAKB_PRAM 0xfe000000 #define SRAM_BASE 0xfc000000 #define SRAM_SIZE 0x1000 #define DPMBA_BASE 0xfa000000 #define DPMBB_BASE 0xfb000000 #define DPMB_SIZE 0x800 #define BOOTROM_BASE 0xfb000000 #define BOOTROM_SIZE 0x400 /* Peripherials */ #define SIAP_BASE (PERIPH_BASE+0) #define SMC_BASE (PERIPH_BASE+0x4000) #define DMC_BASE (PERIPH_BASE+0x8000) #define PIOA_BASE (PERIPH_BASE+0xc000) #define PIOB_BASE (PERIPH_BASE+0x10000) #define KB_BASE (PERIPH_BASE+0x10000) #define TMC_BASE (PERIPH_BASE+0x14000) #define USARTA_BASE (PERIPH_BASE+0x18000) #define USARTB_BASE (PERIPH_BASE+0x1c000) #define SPI_BASE (PERIPH_BASE+0x20000) #define WDG_BASE (PERIPH_BASE+0x28000) #define AIC_BASE (PERIPH_BASE+0x30000) /* SIAP registers */ #define SIAP_MD (SIAP_BASE) #define SIAP_ID (SIAP_BASE+4) #define SIAP_RST (SIAP_BASE+8) /* SIAP mode register */ #define SIAP_SW2 (1<<11) #define SIAP_SW1 (1<<10) #define SIAP_LPCS(x)(x<<8 & 0x300) #define SIAP_LP (1<<6) #define SIAP_CS (1<<5) #define SIAP_IB (1<<4) #define SIAP_IA (1<<3) #define SIAP_RB (1<<2) #define SIAP_RA (1<<1) #define SIAP_RM (1) /* SIAP ID register */ #define SIAP_PKG (1<<31) #define SIAP_VERS (1) /* SIAP reset register */ #define SIAP_RESET (7) /* DRAM Memory controller registers */ #define DMR0 (DMC_BASE + 0) #define DMR1 (DMC_BASE + 4) #define DMC_CR (DMC_BASE + 8) /* DMRx registers */ #define DMR_EMR 1 #define DMR_PS(x) (x<<1 & 6) #define DMR_SZ(x) (x<<3 & 0x18) /* DMR memory control register */ #define DMR_ROR (1<<2) #define DMR_BBR (1<<1) #define DMR_DBW 1 /* Static Memory controller registers */ #define SMC_CSR0 (SMC_BASE + 0) #define SMC_CSR1 (SMC_BASE + 4) #define SMC_CSR2 (SMC_BASE + 8) #define SMC_CSR3 (SMC_BASE + 0xc) #define SMC_MCR (SMC_BASE + 0x24) /* SMC chip select registers */ #define SMC_CSEN (1<<13) #define SMC_BAT (1<<12) #define SMC_TDF(x) (x<<9 & 0xe000) #define SMC_PGS(x) (x<<7 & 0x1800) #define SMC_WSE (1<<5) #define SMC_NWS(x) (x<<2 & 0x1c) #define SMC_DBW(x) (x & 3) /* SMC memory control register */ #define SMC_DRP (1<<4) /* Dual Port Memory A */ #define DPMBA_S0 (DPMBA_BASE + 0x200) #define DPMBA_S1 (DPMBA_BASE + 0x204) #define DPMBA_S2 (DPMBA_BASE + 0x208) #define DPMBA_S3 (DPMBA_BASE + 0x20c) #define DPMBA_S4 (DPMBA_BASE + 0x210) #define DPMBA_S5 (DPMBA_BASE + 0x214) #define DPMBA_S6 (DPMBA_BASE + 0x218) #define DPMBA_S7 (DPMBA_BASE + 0x21c) #define DPMBA_CC (DPMBA_BASE + 0x220) /* Dual Port Memory B */ #define DPMBB_S0 (DPMBB_BASE + 0x200) #define DPMBB_S1 (DPMBB_BASE + 0x204) #define DPMBB_S2 (DPMBB_BASE + 0x208) #define DPMBB_S3 (DPMBB_BASE + 0x20c) #define DPMBB_S4 (DPMBB_BASE + 0x210) #define DPMBB_S5 (DPMBB_BASE + 0x214) #define DPMBB_S6 (DPMBB_BASE + 0x218) #define DPMBB_S7 (DPMBB_BASE + 0x21c) #define DPMBB_CC (DPMBB_BASE + 0x220) /* Timer registers */ #define TC0_BASE (TMC_BASE + 0) #define TC1_BASE (TMC_BASE + 0x40) #define TC2_BASE (TMC_BASE + 0x80) #define TC_OFFSET 0x14000 #define TC_BASE(i) (PERIPH_BASE+TC_OFFSET+(i)*0x40) #define TC_BCR (TMC_BASE + 0xC0) #define TC_BMR (TMC_BASE + 0xC4) #ifndef __ASSEMBLER__ struct trio_timer_channel { unsigned long ccr; // channel control register (WO) unsigned long cmr; // channel mode register (RW) unsigned long reserved[2]; unsigned long cv; // counter value (RW) unsigned long ra; // register A (RW) unsigned long rb; // register B (RW) unsigned long rc; // register C (RW) unsigned long sr; // status register (RO) unsigned long ier; // interrupt enable register (WO) unsigned long idr; // interrupt disable register (WO) unsigned long imr; // interrupt mask register (RO) }; struct trio_timers { struct { struct trio_timer_channel ch; unsigned char padding[0x40-sizeof(struct trio_timer_channel)]; } chans[3]; unsigned long bcr; // block control register (WO) unsigned long bmr; // block mode register (RW) }; #endif /* TC control register */ #define TC_SYNC (1) /* TC mode register */ #define TC2XC2S(x) (x & 0x3) #define TC1XC1S(x) (x<<2 & 0xc) #define TC0XC0S(x) (x<<4 & 0x30) /* TC channel control */ #define TC_CLKEN (1) #define TC_CLKDIS (1<<1) #define TC_SWTRG (1<<2) /* TC interrupts enable/disable/mask and status registers */ #define TC_MTIOB (1<<18) #define TC_MTIOA (1<<17) #define TC_CLKSTA (1<<16) #define TC_ETRGS (1<<7) #define TC_LDRBS (1<<6) #define TC_LDRAS (1<<5) #define TC_CPCS (1<<4) #define TC_CPBS (1<<3) #define TC_CPAS (1<<2) #define TC_LOVRS (1<<1) #define TC_COVFS (1) #ifndef __ASSEMBLER__ /* UART registers */ struct uart_regs{ u_32 cr; // control u_32 mr; // mode u_32 ier; // interrupt enable u_32 idr; // interrupt disable u_32 imr; // interrupt mask u_32 csr; // channel status u_32 rhr; // receive holding u_32 thr; // tramsmit holding u_32 brgr; // baud rate generator u_32 rtor; // rx time-out u_32 ttgr; // tx time-guard u_32 res1; u_32 rpr; // rx pointer u_32 rcr; // rx counter u_32 tpr; // tx pointer u_32 tcr; // tx counter u_32 mc; // modem control u_32 ms; // modem status }; #endif /* US control register */ #define US_SENDA (1<<12) #define US_STTO (1<<11) #define US_STPBRK (1<<10) #define US_STTBRK (1<<9) #define US_RSTSTA (1<<8) #define US_TXDIS (1<<7) #define US_TXEN (1<<6) #define US_RXDIS (1<<5) #define US_RXEN (1<<4) #define US_RSTTX (1<<3) #define US_RSTRX (1<<2) /* US mode register */ #define US_CLK0 (1<<18) #define US_MODE9 (1<<17) #define US_CHMODE(x)(x<<14 & 0xc000) #define US_NBSTOP(x)(x<<12 & 0x3000) #define US_PAR(x) (x<<9 & 0xe00) #define US_SYNC (1<<8) #define US_CHRL(x) (x<<6 & 0xc0) #define US_USCLKS(x)(x<<4 & 0x30) /* US interrupts enable/disable/mask and status register */ #define US_DMSI (1<<10) #define US_TXEMPTY (1<<9) #define US_TIMEOUT (1<<8) #define US_PARE (1<<7) #define US_FRAME (1<<6) #define US_OVRE (1<<5) #define US_ENDTX (1<<4) #define US_ENDRX (1<<3) #define US_RXBRK (1<<2) #define US_TXRDY (1<<1) #define US_RXRDY (1) #define US_ALL_INTS (US_DMSI|US_TXEMPTY|US_TIMEOUT|US_PARE|US_FRAME|US_OVRE|US_ENDTX|US_ENDRX|US_RXBRK|US_TXRDY|US_RXRDY) /* US modem control register */ #define US_FCM (1<<5) #define US_RTS (1<<1) #define US_DTR (1) /* US modem status register */ #define US_FCMS (1<<8) #define US_DCD (1<<7) #define US_RI (1<<6) #define US_DSR (1<<5) #define US_CTS (1<<4) #define US_DDCD (1<<3) #define US_TERI (1<<2) #define US_DDSR (1<<1) #define US_DCTS (1) /* Advanced Interrupt Controller registers */ #define AIC_SMR(i) (AIC_BASE+i*4) #define AIC_IVR (AIC_BASE+0x100) #define AIC_FVR (AIC_BASE+0x104) #define AIC_ISR (AIC_BASE+0x108) #define AIC_IPR (AIC_BASE+0x10C) #define AIC_IMR (AIC_BASE+0x110) #define AIC_CISR (AIC_BASE+0x114) #define AIC_IECR (AIC_BASE+0x120) #define AIC_IDCR (AIC_BASE+0x124) #define AIC_ICCR (AIC_BASE+0x128) #define AIC_ISCR (AIC_BASE+0x12C) #define AIC_EOICR (AIC_BASE+0x130) /* AIC enable/disable/mask/pending registers */ #define AIC_PIOB (1<<15) #define AIC_UB (1<<14) #define AIC_OAKB (1<<13) #define AIC_OAKA (1<<12) #define AIC_IRQ1 (1<<11) #define AIC_IRQ0 (1<<10) #define AIC_SPI (1<<9) #define AIC_LCD (1<<8) #define AIC_PIOA (1<<7) #define AIC_TC2 (1<<6) #define AIC_TC1 (1<<5) #define AIC_TC0 (1<<4) #define AIC_UA (1<<3) #define AIC_SWI (1<<2) #define AIC_WD (1<<1) #define AIC_FIQ (1) /* PIOA registers */ #define PIOA_PER (PIOA_BASE+0) #define PIOA_PDR (PIOA_BASE+0x4) #define PIOA_PSR (PIOA_BASE+0x8) #define PIOA_OER (PIOA_BASE+0x10) #define PIOA_ODR (PIOA_BASE+0x14) #define PIOA_OSR (PIOA_BASE+0x18) #define PIOA_IFER (PIOA_BASE+0x20) #define PIOA_IFDR (PIOA_BASE+0x24) #define PIOA_IFSR (PIOA_BASE+0x28) #define PIOA_SODR (PIOA_BASE+0x30) #define PIOA_CODR (PIOA_BASE+0x34) #define PIOA_ODSR (PIOA_BASE+0x38) #define PIOA_PDSR (PIOA_BASE+0x3C) #define PIOA_IER (PIOA_BASE+0x40) #define PIOA_IDR (PIOA_BASE+0x44) #define PIOA_IMR (PIOA_BASE+0x48) #define PIOA_ISR (PIOA_BASE+0x4C) /* PIOA bit allocation */ #define PIOA_TCLK0 (1<<8) #define PIOA_TI0A0 (1<<9) #define PIOA_TI0B0 (1<<10) #define PIOA_SCLKA (1<<11) #define PIOA_NPCS1 (1<<12) #define PIOA_SCLKB (1<<13) #define PIOA_NPCS2 (1<<14) #define PIOA_NPCS3 (1<<15) #define PIOA_TCLK2 (1<<16) #define PIOA_TIOA2 (1<<17) #define PIOA_TIOB2 (1<<18) #define PIOA_ACLK (1<<19) /* PIOB registers */ #define PIOB_PER (PIOB_BASE+0) #define PIOB_PDR (PIOB_BASE+0x4) #define PIOB_PSR (PIOB_BASE+0x8) #define PIOB_OER (PIOB_BASE+0x10) #define PIOB_ODR (PIOB_BASE+0x14) #define PIOB_OSR (PIOB_BASE+0x18) #define PIOB_IFER (PIOB_BASE+0x20) #define PIOB_IFDR (PIOB_BASE+0x24) #define PIOB_IFSR (PIOB_BASE+0x28) #define PIOB_SODR (PIOB_BASE+0x30) #define PIOB_CODR (PIOB_BASE+0x34) #define PIOB_ODSR (PIOB_BASE+0x38) #define PIOB_PDSR (PIOB_BASE+0x3C) #define PIOB_IER (PIOB_BASE+0x40) #define PIOB_IDR (PIOB_BASE+0x44) #define PIOB_IMR (PIOB_BASE+0x48) #define PIOB_ISR (PIOB_BASE+0x4C) /* PIOB bit allocation */ #define PIOB_TCLK1 (1) #define PIOB_TIOA1 (1<<1) #define PIOB_TIOB1 (1<<2) #define PIOB_NCTSA (1<<3) #define PIOB_NRIA (1<<5) #define PIOB_NWDOVF (1<<6) #define PIOB_NCE1 (1<<7) #define PIOB_NCE2 (1<<8) #ifndef __ASSEMBLER__ struct pio_regs{ u_32 per; u_32 pdr; u_32 psr; u_32 res1; u_32 oer; u_32 odr; u_32 osr; u_32 res2; u_32 ifer; u_32 ifdr; u_32 ifsr; u_32 res3; u_32 sodr; u_32 codr; u_32 odsr; u_32 pdsr; u_32 ier; u_32 idr; u_32 imr; u_32 isr; }; #endif /* Serial Peripheral Interface */ #define SP_CR (SPI_BASE + 0) #define SP_MR (SPI_BASE + 4) #define SP_RDR (SPI_BASE + 8) #define SP_TDR (SPI_BASE + 0xC) #define SP_SR (SPI_BASE + 0x10) #define SP_IER (SPI_BASE + 0x14) #define SP_IDR (SPI_BASE + 0x18) #define SP_IMR (SPI_BASE + 0x1C) #define SP_CSR0 (SPI_BASE + 0x30) #define SP_CSR1 (SPI_BASE + 0x34) #define SP_CSR2 (SPI_BASE + 0x38) #define SP_CSR3 (SPI_BASE + 0x3C) #ifndef __ASSEMBLER__ struct spi_regs{ u_32 cr; u_32 mr; u_32 rdr; u_32 tdr; u_32 sr; u_32 ier; u_32 idr; u_32 imr; u_32 res1; u_32 res2; u_32 res3; u_32 res4; u_32 csr0; u_32 csr1; u_32 csr2; u_32 csr3; }; #endif /* SPI control register */ #define SPI_SWRST (1<<7) #define SPI_SPIDIS (1<<1) #define SPI_SPIEN (1) /* SPI mode register */ #define SPI_MSTR (1) #define SPI_PS (1<<1) #define SPI_PCSDEC (1<<2) #define SPI_MCSK32 (1<<3) #define SPI_LLB (1<<7) #define SPI_PCS(x) (x<<16 & 0xF0000) #define SPI_DLYBCS(x) (x<<24 & 0xFF000000) /* SPI Receive/Transmit Data Register */ #define SPI_PCS_MASK (0xF0000) /* SPI Interrupt enable/disable and Status registers */ #define SPI_OVRES (1<<3) #define SPI_MODF (1<<2) #define SPI_TDRE (1<<1) #define SPI_RDRF (1) /* SPI chip selects registers */ #define SPI_CPOL (1) #define SPI_NCPHA (1<<1) #define SPI_BITS_MASK 0xF0 #define SPI_SCBR_MASK 0xF00 #define SPI_DLYBS_MASK 0xF0000 #define SPI_DLYBCT_MASK 0xF000000 #define SPI_BITS(x) (x<<4 & SPI_BITS_MASK) #define SPI_SCBR(x) (x<<8 & SPI_SCBR_MASK) #define SPI_DLYBS(x) (x<<16 & SPI_DLYBS_MASK) #define SPI_DLYBCT(x) (x<<24 & SPI_DLYBCT_MASK) /* Watchdog registers */ #define WDG_OMR (WD_BASE + 0) #define WDG_CMR (WD_BASE + 4) #define WDG_CR (WD_BASE + 8) #define WDG_SR (WD_BASE + 0xC) /* Overflow Mode Register */ #define WDG_OKEY_MASK 0xFFF0 #define WDG_OKEY(x) (x<<4 & WDG_OKEY_MASK) #define WDG_EXTEN (1<<3) #define WDG_IRQEN (1<<2) #define WDG_RSTEN (1<<1) #define WDG_WDEN (1) /* Clock Mode Register */ #define WDG_CKEY_MASK 0xFF80 #define WDG_HPCV_MASK 0x3C #define WDG_WDCLKS_MASK 0x3 #define WDG_CKEY(x) (x<<7 & WDG_CKEY_MASK) #define WDG_HPCV(x) (x<<2 & WDG_HPCV_MASK) #define WDG_WDCLKS(x) (x & WDG_WDCLKS_MASK) /* Control Register */ #define WDG_RESTART_KEY 0xC071 /* Status Register */ #define WDG_WDOVF (1) #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/io.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/io.h?rev=1.1&content-type=text/x-cvsweb-markup Index: io.h =================================================================== /* * linux/include/asm-arm/arch-a5k/io.h * * Copyright (C) 1997 Russell King * Copyright (C) 1999 Aplio SA * * Modifications: * 06-Dec-1997 RMK Created. */ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H /* * This architecture does not require any delayed IO, and * has the constant-optimised IO */ #undef ARCH_IO_DELAY #if 0 /* * We use two different types of addressing - PC style addresses, and ARM * addresses. PC style accesses the PC hardware with the normal PC IO * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ * and are translated to the start of IO. Note that all addresses are * shifted left! */ #define __PORT_PCIO(x) (!((x) & 0x80000000)) /* * Dynamic IO functions - let the compiler * optimize the expressions */ extern __inline__ void __outb (unsigned int value, unsigned int port) { unsigned long temp; __asm__ __volatile__( "tst %2, #0x80000000\n\t" "mov %0, %4\n\t" "addeq %0, %0, %3\n\t" "strb %1, [%0, %2, lsl #2]" : "=&r" (temp) : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) : "cc"); } extern __inline__ void __outw (unsigned int value, unsigned int port) { unsigned long temp; __asm__ __volatile__( "tst %2, #0x80000000\n\t" "mov %0, %4\n\t" "addeq %0, %0, %3\n\t" "str %1, [%0, %2, lsl #2]" : "=&r" (temp) : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) : "cc"); } extern __inline__ void __outl (unsigned int value, unsigned int port) { unsigned long temp; __asm__ __volatile__( "tst %2, #0x80000000\n\t" "mov %0, %4\n\t" "addeq %0, %0, %3\n\t" "str %1, [%0, %2, lsl #2]" : "=&r" (temp) : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) : "cc"); } #define DECLARE_DYN_IN(sz,fnsuffix,instr) \ extern __inline__ unsigned sz __in##fnsuffix (unsigned int port) \ { \ unsigned long temp, value; \ __asm__ __volatile__( \ "tst %2, #0x80000000\n\t" \ "mov %0, %4\n\t" \ "addeq %0, %0, %3\n\t" \ "ldr" ##instr## " %1, [%0, %2, lsl #2]" \ : "=&r" (temp), "=r" (value) \ : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \ : "cc"); \ return (unsigned sz)value; \ } extern __inline__ unsigned int __ioaddr (unsigned int port) \ { \ if (__PORT_PCIO(port)) \ return (unsigned int)(PCIO_BASE + (port << 2)); \ else \ return (unsigned int)(IO_BASE + (port << 2)); \ } #undef DECLARE_DYN_IN /* * Constant address IO functions * * These have to be macros for the 'J' constraint to work - * +/-4096 immediate operand. */ #define __outbc(value,port) \ ({ \ if (__PORT_PCIO((port))) \ __asm__ __volatile__( \ "strb %0, [%1, %2]" \ : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ else \ __asm__ __volatile__( \ "strb %0, [%1, %2]" \ : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \ }) #define __inbc(port) \ ({ \ unsigned char result; \ if (__PORT_PCIO((port))) \ __asm__ __volatile__( \ "ldrb %0, [%1, %2]" \ : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ else \ __asm__ __volatile__( \ "ldrb %0, [%1, %2]" \ : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ result; \ }) #define __outwc(value,port) \ ({ \ unsigned long v = value; \ if (__PORT_PCIO((port))) \ __asm__ __volatile__( \ "str %0, [%1, %2]" \ : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ else \ __asm__ __volatile__( \ "str %0, [%1, %2]" \ : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \ }) #define __inwc(port) \ ({ \ unsigned short result; \ if (__PORT_PCIO((port))) \ __asm__ __volatile__( \ "ldr %0, [%1, %2]" \ : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ else \ __asm__ __volatile__( \ "ldr %0, [%1, %2]" \ : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ result & 0xffff; \ }) #define __outlc(v,p) __outwc((v),(p)) #define __inlc(port) \ ({ \ unsigned long result; \ if (__PORT_PCIO((port))) \ __asm__ __volatile__( \ "ldr %0, [%1, %2]" \ : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ else \ __asm__ __volatile__( \ "ldr %0, [%1, %2]" \ : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ result; \ }) #define __ioaddrc(port) \ ({ \ unsigned long addr; \ if (__PORT_PCIO((port))) \ addr = PCIO_BASE + ((port) << 2); \ else \ addr = IO_BASE + ((port) << 2); \ addr; \ }) #else /* * Translated address IO functions * * IO address has already been translated to a virtual address */ #define outb_t(v,p) (*(volatile unsigned char *)(p) = (v)) #define outw_t(v,p) (*(volatile unsigned short *)(p) = (v)) #define outl_t(v,p) (*(volatile unsigned long *)(p) = (v)) #define inb_t(p) (*(volatile unsigned char *)(p)) #define inw_t(p) (*(volatile unsigned short *)(p)) #define inl_t(p) (*(volatile unsigned long *)(p)) extern __inline__ void __outb (unsigned int value, unsigned int port) { outb_t(value,port); } extern __inline__ void __outw (unsigned int value, unsigned int port) { outw_t(value,port); } extern __inline__ void __outl (unsigned int value, unsigned int port) { outl_t(value,port); } #define DECLARE_DYN_IN(sz,fnsuffix,instr) \ extern __inline__ unsigned sz __in##fnsuffix (unsigned int port) { return in##fnsuffix##_t(port); } DECLARE_DYN_IN(char,b,"b") DECLARE_DYN_IN(short,w,"") DECLARE_DYN_IN(long,l,"") #undef DECLARE_DYN_IN #define __outbc(value,port) outb_t(value,port) #define __outwc(value,port) outw_t(value,port) #define __outlc(value,port) outl_t(value,port) #endif #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/irq.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/irq.h?rev=1.1&content-type=text/x-cvsweb-markup Index: irq.h =================================================================== /* * include/asm-arm/arch-trio/irq.h * * Copyright (C) 1996 Russell King * Copyright (C) 1999 APLIO SA * * Changelog: * 04-11-1999 VL Created */ #define BUILD_IRQ(s,n,m) struct pt_regs; extern int IRQ_interrupt(int irq, struct pt_regs *regs); extern int timer_IRQ_interrupt(int irq, struct pt_regs *regs); extern int fast_IRQ_interrupt(int irq, struct pt_regs *regs); extern int bad_IRQ_interrupt(int irq, struct pt_regs *regs); extern int probe_IRQ_interrupt(int irq, struct pt_regs *regs); #define IRQ_interrupt0 IRQ_interrupt #define IRQ_interrupt1 IRQ_interrupt #define IRQ_interrupt2 IRQ_interrupt #define IRQ_interrupt3 IRQ_interrupt #define IRQ_interrupt4 IRQ_interrupt #define IRQ_interrupt5 timer_IRQ_interrupt #define IRQ_interrupt4 IRQ_interrupt #define IRQ_interrupt6 IRQ_interrupt #define IRQ_interrupt7 IRQ_interrupt #define IRQ_interrupt8 IRQ_interrupt #define IRQ_interrupt9 IRQ_interrupt #define IRQ_interrupt10 IRQ_interrupt #define IRQ_interrupt11 IRQ_interrupt #define IRQ_interrupt12 IRQ_interrupt #define IRQ_interrupt13 IRQ_interrupt #define IRQ_interrupt14 IRQ_interrupt #define IRQ_interrupt15 IRQ_interrupt #define IRQ_interrupt16 IRQ_interrupt #define IRQ_interrupt17 IRQ_interrupt #define IRQ_interrupt18 IRQ_interrupt #define IRQ_interrupt19 IRQ_interrupt #define IRQ_interrupt20 IRQ_interrupt #define IRQ_interrupt21 IRQ_interrupt #define IRQ_interrupt22 IRQ_interrupt #define IRQ_interrupt23 IRQ_interrupt #define IRQ_INTERRUPT(n) (void (*)(void))IRQ_interrupt##n #define FAST_INTERRUPT(n) (void (*)(void))fast_IRQ_interrupt #define BAD_INTERRUPT(n) (void (*)(void))bad_IRQ_interrupt #define PROBE_INTERRUPT(n) (void (*)(void))probe_IRQ_interrupt static __inline__ void mask_irq(unsigned int irq) { unsigned long mask = 1 << (irq & 0xf); outl(mask, AIC_IDCR); } static __inline__ void unmask_irq(unsigned int irq) { unsigned long mask = 1 << (irq & 0xf); outl(mask, AIC_IECR); } static __inline__ unsigned long get_enabled_irqs(void) { return inl(AIC_IMR); } static __inline__ void irq_init_irq(void) { extern void trio_init_aic(); trio_init_aic(); } 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/irqs.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/irqs.h?rev=1.1&content-type=text/x-cvsweb-markup Index: irqs.h =================================================================== /* * linux/include/asm-arm/arch-a5k/irqs.h * * Copyright (C) 1996 Russell King */ #define IRQ_FIQ 0 #define IRQ_WD 1 #define IRQ_SWI 2 #define IRQ_USARTA 3 #define IRQ_TC0 4 #define IRQ_TC1 5 #define IRQ_TC2 6 #define IRQ_PIOA 7 #define IRQ_LCD 8 #define IRQ_SPI 9 #define IRQ_EXT0 10 #define IRQ_EXT1 11 #define IRQ_OAKA 12 #define IRQ_OAKB 13 #define IRQ_USARTB 14 #define IRQ_PIOB 15 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/mmu.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/mmu.h?rev=1.1&content-type=text/x-cvsweb-markup Index: mmu.h =================================================================== /* * linux/include/asm-arm/arch-a5k/mmu.h * * Copyright (c) 1996 Russell King. * * Changelog: * 22-11-1996 RMK Created */ #ifndef __ASM_ARCH_MMU_H #define __ASM_ARCH_MMU_H #define __virt_to_phys__is_a_macro #define __virt_to_phys(vpage) vpage #define __phys_to_virt__is_a_macro #define __phys_to_virt(ppage) ppage #define __virt_to_bus__is_a_macro #define __virt_to_bus(vpage) vpage #define __bus_to_virt__is_a_macro #define __bus_to_virt(ppage) ppage #define __flush_entry_to_ #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/oldlatches.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/oldlatches.h?rev=1.1&content-type=text/x-cvsweb-markup Index: oldlatches.h =================================================================== /* * Dummy oldlatches.h * * Copyright (C) 1996 Russell King */ #ifdef __need_oldlatches #error "Old latches not present in this (a5k) machine" #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/processor.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/processor.h?rev=1.1&content-type=text/x-cvsweb-markup Index: processor.h =================================================================== /* * linux/include/asm-arm/arch-a5k/processor.h * * Copyright (c) 1996 Russell King. * * Changelog: * 10-09-1996 RMK Created */ #ifndef __ASM_ARCH_PROCESSOR_H #define __ASM_ARCH_PROCESSOR_H /* * Bus types */ #define EISA_bus 0 #define EISA_bus__is_a_macro /* for versions in ksyms.c */ #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ /* * User space: 26MB */ #define TASK_SIZE (0x01a00000UL) #define INIT_MMAP { &init_mm, 0, 0x02000000, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC } #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/serial.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/serial.h?rev=1.1&content-type=text/x-cvsweb-markup Index: serial.h =================================================================== /* * linux/include/asm-arm/arch-a5k/serial.h * * Copyright (c) 1996 Russell King. * * Changelog: * 15-10-1996 RMK Created */ #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H /* * This assumes you have a 1.8432 MHz clock for your UART. * * It'd be nice if someone built a serial card with a 24.576 MHz * clock, since the 16550A is capable of handling a top speed of 1.5 * megabits/second; but this requires the faster clock. */ #define BASE_BAUD (1843200 / 16) #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) /* UART CLK PORT IRQ FLAGS */ #define RS_UARTS \ { 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS }, /* ttyS0 */ \ { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS } /* ttyS1 */ #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/shmparam.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/shmparam.h?rev=1.1&content-type=text/x-cvsweb-markup Index: shmparam.h =================================================================== /* * linux/include/asm-arm/arch-a5k/shmparam.h * * Copyright (c) 1996 Russell King. */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/system.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/system.h?rev=1.1&content-type=text/x-cvsweb-markup Index: system.h =================================================================== /* * linux/include/asm-arm/arch-trio/system.h * * Copyright (c) 1996 Russell King */ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H #include <asm/hardware.h> #include <asm/io.h> extern __inline__ void arch_hard_reset (void) { outl((1 << 11) | 1, SIAP_RST); while (1); } #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/time.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/time.h?rev=1.1&content-type=text/x-cvsweb-markup Index: time.h =================================================================== /* * linux/include/asm-arm/arch-trio/time.h * * Copyright (c) 1996 Russell King. * * Changelog: * 24-Sep-1996 RMK Created * 10-Oct-1996 RMK Brought up to date with arch-sa110eval * 04-Dec-1997 RMK Updated for new arch/arm/time.c */ extern __inline__ unsigned long gettimeoffset (void) { struct trio_timers* tt = (struct trio_timers*) (PERIPH_BASE+TC_OFFSET); struct trio_timer_channel* tc = &tt->chans[1].ch; return tc->cv * (ARM_CLK/128); } #if 0 { unsigned int count1, count2, status1, status2; unsigned long offset = 0; status1 = inb(IOC_IRQREQA); barrier (); outb (0, IOC_T0LATCH); barrier (); count1 = inb(IOC_T0CNTL) | (inb(IOC_T0CNTH) << 8); barrier (); status2 = inb(IOC_IRQREQA); barrier (); outb (0, IOC_T0LATCH); barrier (); count2 = inb(IOC_T0CNTL) | (inb(IOC_T0CNTH) << 8); if (count2 < count1) { /* * This means that we haven't just had an interrupt * while reading into status2. */ if (status2 & (1 << 5)) offset = tick; count1 = count2; } else if (count2 > count1) { /* * We have just had another interrupt while reading * status2. */ offset += tick; count1 = count2; } count1 = LATCH - count1; /* * count1 = number of clock ticks since last interrupt */ offset += count1 * tick / LATCH; return offset; } #endif /* * No need to reset the timer at every irq */ extern __inline__ int reset_timer() { struct trio_timers* tt = (struct trio_timers*) (PERIPH_BASE+TC_OFFSET); volatile struct trio_timer_channel* tc = &tt->chans[1].ch; unsigned long v = tc->sr; return (1); } /* * Updating of the RTC. We don't currently write the time to the * CMOS clock. */ #define update_rtc() /* * Set up timer interrupt, and return the current time in seconds. */ extern __inline__ unsigned long setup_timer (void) { register volatile struct trio_timers* tt = (struct trio_timers*) (PERIPH_BASE+TC_OFFSET); register volatile struct trio_timer_channel* tc = &tt->chans[1].ch; unsigned long v; /* program NO signal on XC1 */ v = tt->bcr; v = (v & ~(3 << 2)) | (1 << 2); tt->bcr = v; tc->ccr = 0x20; /* disable the channel */ /* select ACLK/128 as inupt frequensy for TC1 */ tc->cmr = 3; tc->idr = ~0ul; /* disable all interrupt */ tc->ier = 1 << 4; /* enable CPCS interrupt */ tc->rc = ((ARM_CLK/128)/HZ - 1); /* load the count limit into the CR register */ /* enable the channel */ tc->ccr = 1; return mktime(1999, 11, 1, 0, 0, 0); } #if 0 { extern int iic_control (unsigned char, int, char *, int); unsigned int year, mon, day, hour, min, sec; char buf[8]; outb(LATCH & 255, IOC_T0LTCHL); outb(LATCH >> 8, IOC_T0LTCHH); outb(0, IOC_T0GO); iic_control (0xa0, 0xc0, buf, 1); year = buf[0]; if ((year += 1900) < 1970) year += 100; iic_control (0xa0, 2, buf, 5); mon = buf[4] & 0x1f; day = buf[3] & 0x3f; hour = buf[2]; min = buf[1]; sec = buf[0]; BCD_TO_BIN(mon); BCD_TO_BIN(day); BCD_TO_BIN(hour); BCD_TO_BIN(min); BCD_TO_BIN(sec); return mktime(year, mon, day, hour, min, sec); } #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/uncompress.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-armnommu/arch-trio/uncompress.h?rev=1.1&content-type=text/x-cvsweb-markup Index: uncompress.h =================================================================== /* * linux/include/asm-arm/arch-a5k/uncompress.h * * Copyright (C) 1996 Russell King */ #define VIDMEM ((char *)0x02000000) #include "../arch/arm/drivers/char/font.h" int video_num_columns, video_num_lines, video_size_row; int white, bytes_per_char_h; extern unsigned long con_charconvtable[256]; struct param_struct { unsigned long page_size; unsigned long nr_pages; unsigned long ramdisk_size; unsigned long mountrootrdonly; unsigned long rootdev; unsigned long video_num_cols; unsigned long video_num_rows; unsigned long video_x; unsigned long video_y; unsigned long memc_control_reg; unsigned char sounddefault; unsigned char adfsdrives; unsigned char bytes_per_char_h; unsigned char bytes_per_char_v; unsigned long unused[256/4-11]; }; static struct param_struct *params = (struct param_struct *)0x0; /* * This does not append a newline */ static void puts(const char *s) { #if 0 extern void ll_write_char(char *, unsigned long); int x,y; unsigned char c; char *ptr; x = params->video_x; y = params->video_y; while ( ( c = *(unsigned char *)s++ ) != '\0' ) { if ( c == '\n' ) { x = 0; if ( ++y >= video_num_lines ) { y--; } } else { ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h); ll_write_char(ptr, c|(white<<8)); if ( ++x >= video_num_columns ) { x = 0; if ( ++y >= video_num_lines ) { y--; } } } } params->video_x = x; params->video_y = y; #endif } static void error(char *x); /* * Setup for decompression */ static void arch_decomp_setup(void) { int i; video_num_lines = params->video_num_rows; video_num_columns = params->video_num_cols; bytes_per_char_h = params->bytes_per_char_h; video_size_row = video_num_columns * bytes_per_char_h; if (bytes_per_char_h == 4) for (i = 0; i < 256; i++) con_charconvtable[i] = (i & 128 ? 1 << 0 : 0) | (i & 64 ? 1 << 4 : 0) | (i & 32 ? 1 << 8 : 0) | (i & 16 ? 1 << 12 : 0) | (i & 8 ? 1 << 16 : 0) | (i & 4 ? 1 << 20 : 0) | (i & 2 ? 1 << 24 : 0) | (i & 1 ? 1 << 28 : 0); else for (i = 0; i < 16; i++) con_charconvtable[i] = (i & 8 ? 1 << 0 : 0) | (i & 4 ? 1 << 8 : 0) | (i & 2 ? 1 << 16 : 0) | (i & 1 ? 1 << 24 : 0); white = bytes_per_char_h == 8 ? 0xfc : 7; if (params->nr_pages * params->page_size < 4096*1024) error("<4M of mem\n"); }

     
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