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From: cvs at opencores.org<cvs@o...>
Date: Tue Dec 20 12:20:32 CET 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/12 20:12:20

Added: or1k/rc203soc/sw/uClinux/include/asm-alpha a.out.h apecs.h
atomic.h bitops.h bugs.h byteorder.h checksum.h
cia.h console.h delay.h dma.h elf.h errno.h fcntl.h
floppy.h fpu.h gentrap.h hwrpb.h io.h ioctl.h
ioctls.h ipsum.h irq.h jensen.h lca.h mman.h
mmu_context.h page.h pal.h param.h pgtable.h
posix_types.h processor.h ptrace.h pyxis.h reg.h
resource.h segment.h semaphore.h shmparam.h
sigcontext.h signal.h socket.h sockios.h stat.h
statfs.h string.h system.h t2.h termbits.h
termios.h types.h unaligned.h unistd.h user.h
Log:
First Import of RC20x uClinux


Revision Changes Path
1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/a.out.h

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/a.out.h?rev=1.1&content-type=text/x-cvsweb-markup

Index: a.out.h
===================================================================
#ifndef __ALPHA_A_OUT_H__
#define __ALPHA_A_OUT_H__

#include <linux/types.h>

/*
* OSF/1 ECOFF header structs. ECOFF files consist of:
* - a file header (struct filehdr),
* - an a.out header (struct aouthdr),
* - one or more section headers (struct scnhdr).
* The filhdr's "f_nscns" field contains the
* number of section headers.
*/

struct filehdr
{
/* OSF/1 "file" header */
__u16 f_magic, f_nscns;
__u32 f_timdat;
__u64 f_symptr;
__u32 f_nsyms;
__u16 f_opthdr, f_flags;
};

struct aouthdr
{
__u64 info; /* after that it looks quite normal.. */
__u64 tsize;
__u64 dsize;
__u64 bsize;
__u64 entry;
__u64 text_start; /* with a few additions that actually make sense */
__u64 data_start;
__u64 bss_start;
__u32 gprmask, fprmask; /* bitmask of general & floating point regs used in binary */
__u64 gpvalue;
};

struct scnhdr
{
char s_name[8];
__u64 s_paddr;
__u64 s_vaddr;
__u64 s_size;
__u64 s_scnptr;
__u64 s_relptr;
__u64 s_lnnoptr;
__u16 s_nreloc;
__u16 s_nlnno;
__u32 s_flags;
};

struct exec
{
/* OSF/1 "file" header */
struct filehdr fh;
struct aouthdr ah;
};

/*
* Define's so that the kernel exec code can access the a.out header
* fields...
*/
#define a_info ah.info
#define a_text ah.tsize
#define a_data ah.dsize
#define a_bss ah.bsize
#define a_entry ah.entry
#define a_textstart ah.text_start
#define a_datastart ah.data_start
#define a_bssstart ah.bss_start
#define a_gprmask ah.gprmask
#define a_fprmask ah.fprmask
#define a_gpvalue ah.gpvalue

#define N_TXTADDR(x) ((x).a_textstart)
#define N_DATADDR(x) ((x).a_datastart)
#define N_BSSADDR(x) ((x).a_bssstart)
#define N_DRSIZE(x) 0 #define N_TRSIZE(x) 0 #define N_SYMSIZE(x) 0 #define AOUTHSZ sizeof(struct aouthdr) #define SCNHSZ sizeof(struct scnhdr) #define SCNROUND 16 #define N_TXTOFF(x) \ ((long) N_MAGIC(x) == ZMAGIC ? 0 : \ (sizeof(struct exec) + (x).fh.f_nscns*SCNHSZ + SCNROUND - 1) & ~(SCNROUND - 1)) #ifdef __KERNEL__ #define STACK_TOP ((current->personality & ADDR_MAX_32BIT) ? 0x100000000UL : \ ((current->personality&ADDR_MAX_31BIT) ? 0x80000000UL : 0x00120000000UL)) #endif #endif /* __A_OUT_GNU_H__ */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/apecs.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/apecs.h?rev=1.1&content-type=text/x-cvsweb-markup Index: apecs.h =================================================================== #ifndef __ALPHA_APECS__H__ #define __ALPHA_APECS__H__ #include <linux/types.h> /* * APECS is the internal name for the 2107x chipset which provides * memory controller and PCI access for the 21064 chip based systems. * * This file is based on: * * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets * Data Sheet * * EC-N0648-72 * * * david.rusling@r... Initial Version. * */ #include <linux/config.h> #ifdef CONFIG_ALPHA_XL /* An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address that get passed through the PCI<->ISA bridge chip. So we've gotta use both windows to max out the physical memory we can DMA to. Sigh... If we try a window at 0 for 1GB as a work-around, we run into conflicts with ISA/PCI bus memory which can't be relocated, like VGA aperture and BIOS ROMs. So we must put the windows high enough to avoid these areas. We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1, and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1. Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually be used for that range (via virt_to_bus()). Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb, to keep virt_to_bus() from returning an address in the first window, for a data area that goes beyond the 64Mb first DMA window. Sigh... The fudge factor MUST match with <asm/dma.h> MAX_DMA_ADDRESS, but we can't just use that here, because of header file looping... :-( Window 1 will be used for all DMA from the ISA bus; yes, that does limit what memory an ISA floppy or soundcard or Ethernet can touch, but it's also a known limitation on other platforms as well. We use the same technique that is used on INTEL platforms with similar limitation: set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init(). We trust that any ISA bus device drivers will *always* ask for DMAable memory explicitly via kmalloc()/get_free_pages() flags arguments. Note that most PCI bus devices' drivers do *not* explicitly ask for DMAable memory; they count on being able to DMA to any memory they get from kmalloc()/get_free_pages(). They will also use window 1 for any physical memory accesses below 64Mb; the rest will be handled by window 2, maxing out at 1Gb of memory. I trust this is enough... :-) We hope that the area before the first window is large enough so that there will be no overlap at the top end (64Mb). We *must* locate the PCI cards' memory just below window 1, so that there's still the possibility of being able to access it via SPARSE space. This is important for cards such as the Matrox Millennium, whose Xserver wants to access memory-mapped registers in byte and short lengths. Note that the XL is treated differently from the AVANTI, even though for most other things they are identical. It didn't seem reasonable to make the AVANTI support pay for the limitations of the XL. It is true, however, that an XL kernel will run on an AVANTI without problems. */ #define APECS_XL_DMA_WIN1_BASE (64*1024*1024) #define APECS_XL_DMA_WIN1_SIZE (64*1024*1024) #define APECS_XL_DMA_WIN1_SIZE_PARANOID (48*1024*1024) #define APECS_XL_DMA_WIN2_BASE (1024*1024*1024) #define APECS_XL_DMA_WIN2_SIZE (1024*1024*1024) #else /* CONFIG_ALPHA_XL */ /* these are for normal APECS family machines, AVANTI/MUSTANG/EB64/PC64 */ #ifdef CONFIG_ALPHA_SRM_SETUP /* if we are using the SRM PCI setup, we'll need to use variables instead */ #define APECS_DMA_WIN_BASE_DEFAULT (1024*1024*1024) #define APECS_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) extern unsigned int APECS_DMA_WIN_BASE; extern unsigned int APECS_DMA_WIN_SIZE; #else /* SRM_SETUP */ #define APECS_DMA_WIN_BASE (1024*1024*1024) #define APECS_DMA_WIN_SIZE (1024*1024*1024) #endif /* SRM_SETUP */ #endif /* CONFIG_ALPHA_XL */ /* * 21071-DA Control and Status registers. * These are used for PCI memory access. */ #define APECS_IOC_DCSR (IDENT_ADDR + 0x1A0000000UL) #define APECS_IOC_PEAR (IDENT_ADDR + 0x1A0000020UL) #define APECS_IOC_SEAR (IDENT_ADDR + 0x1A0000040UL) #define APECS_IOC_DR1 (IDENT_ADDR + 0x1A0000060UL) #define APECS_IOC_DR2 (IDENT_ADDR + 0x1A0000080UL) #define APECS_IOC_DR3 (IDENT_ADDR + 0x1A00000A0UL) #define APECS_IOC_TB1R (IDENT_ADDR + 0x1A00000C0UL) #define APECS_IOC_TB2R (IDENT_ADDR + 0x1A00000E0UL) #define APECS_IOC_PB1R (IDENT_ADDR + 0x1A0000100UL) #define APECS_IOC_PB2R (IDENT_ADDR + 0x1A0000120UL) #define APECS_IOC_PM1R (IDENT_ADDR + 0x1A0000140UL) #define APECS_IOC_PM2R (IDENT_ADDR + 0x1A0000160UL) #define APECS_IOC_HAXR0 (IDENT_ADDR + 0x1A0000180UL) #define APECS_IOC_HAXR1 (IDENT_ADDR + 0x1A00001A0UL) #define APECS_IOC_HAXR2 (IDENT_ADDR + 0x1A00001C0UL) #define APECS_IOC_PMLT (IDENT_ADDR + 0x1A00001E0UL) #define APECS_IOC_TLBTAG0 (IDENT_ADDR + 0x1A0000200UL) #define APECS_IOC_TLBTAG1 (IDENT_ADDR + 0x1A0000220UL) #define APECS_IOC_TLBTAG2 (IDENT_ADDR + 0x1A0000240UL) #define APECS_IOC_TLBTAG3 (IDENT_ADDR + 0x1A0000260UL) #define APECS_IOC_TLBTAG4 (IDENT_ADDR + 0x1A0000280UL) #define APECS_IOC_TLBTAG5 (IDENT_ADDR + 0x1A00002A0UL) #define APECS_IOC_TLBTAG6 (IDENT_ADDR + 0x1A00002C0UL) #define APECS_IOC_TLBTAG7 (IDENT_ADDR + 0x1A00002E0UL) #define APECS_IOC_TLBDATA0 (IDENT_ADDR + 0x1A0000300UL) #define APECS_IOC_TLBDATA1 (IDENT_ADDR + 0x1A0000320UL) #define APECS_IOC_TLBDATA2 (IDENT_ADDR + 0x1A0000340UL) #define APECS_IOC_TLBDATA3 (IDENT_ADDR + 0x1A0000360UL) #define APECS_IOC_TLBDATA4 (IDENT_ADDR + 0x1A0000380UL) #define APECS_IOC_TLBDATA5 (IDENT_ADDR + 0x1A00003A0UL) #define APECS_IOC_TLBDATA6 (IDENT_ADDR + 0x1A00003C0UL) #define APECS_IOC_TLBDATA7 (IDENT_ADDR + 0x1A00003E0UL) #define APECS_IOC_TBIA (IDENT_ADDR + 0x1A0000400UL) /* * 21071-CA Control and Status registers. * These are used to program memory timing, * configure memory and initialise the B-Cache. */ #define APECS_MEM_GCR (IDENT_ADDR + 0x180000000UL) #define APECS_MEM_EDSR (IDENT_ADDR + 0x180000040UL) #define APECS_MEM_TAR (IDENT_ADDR + 0x180000060UL) #define APECS_MEM_ELAR (IDENT_ADDR + 0x180000080UL) #define APECS_MEM_EHAR (IDENT_ADDR + 0x1800000a0UL) #define APECS_MEM_SFT_RST (IDENT_ADDR + 0x1800000c0UL) #define APECS_MEM_LDxLAR (IDENT_ADDR + 0x1800000e0UL) #define APECS_MEM_LDxHAR (IDENT_ADDR + 0x180000100UL) #define APECS_MEM_GTR (IDENT_ADDR + 0x180000200UL) #define APECS_MEM_RTR (IDENT_ADDR + 0x180000220UL) #define APECS_MEM_VFPR (IDENT_ADDR + 0x180000240UL) #define APECS_MEM_PDLDR (IDENT_ADDR + 0x180000260UL) #define APECS_MEM_PDhDR (IDENT_ADDR + 0x180000280UL) /* Bank x Base Address Register */ #define APECS_MEM_B0BAR (IDENT_ADDR + 0x180000800UL) #define APECS_MEM_B1BAR (IDENT_ADDR + 0x180000820UL) #define APECS_MEM_B2BAR (IDENT_ADDR + 0x180000840UL) #define APECS_MEM_B3BAR (IDENT_ADDR + 0x180000860UL) #define APECS_MEM_B4BAR (IDENT_ADDR + 0x180000880UL) #define APECS_MEM_B5BAR (IDENT_ADDR + 0x1800008A0UL) #define APECS_MEM_B6BAR (IDENT_ADDR + 0x1800008C0UL) #define APECS_MEM_B7BAR (IDENT_ADDR + 0x1800008E0UL) #define APECS_MEM_B8BAR (IDENT_ADDR + 0x180000900UL) /* Bank x Configuration Register */ #define APECS_MEM_B0BCR (IDENT_ADDR + 0x180000A00UL) #define APECS_MEM_B1BCR (IDENT_ADDR + 0x180000A20UL) #define APECS_MEM_B2BCR (IDENT_ADDR + 0x180000A40UL) #define APECS_MEM_B3BCR (IDENT_ADDR + 0x180000A60UL) #define APECS_MEM_B4BCR (IDENT_ADDR + 0x180000A80UL) #define APECS_MEM_B5BCR (IDENT_ADDR + 0x180000AA0UL) #define APECS_MEM_B6BCR (IDENT_ADDR + 0x180000AC0UL) #define APECS_MEM_B7BCR (IDENT_ADDR + 0x180000AE0UL) #define APECS_MEM_B8BCR (IDENT_ADDR + 0x180000B00UL) /* Bank x Timing Register A */ #define APECS_MEM_B0TRA (IDENT_ADDR + 0x180000C00UL) #define APECS_MEM_B1TRA (IDENT_ADDR + 0x180000C20UL) #define APECS_MEM_B2TRA (IDENT_ADDR + 0x180000C40UL) #define APECS_MEM_B3TRA (IDENT_ADDR + 0x180000C60UL) #define APECS_MEM_B4TRA (IDENT_ADDR + 0x180000C80UL) #define APECS_MEM_B5TRA (IDENT_ADDR + 0x180000CA0UL) #define APECS_MEM_B6TRA (IDENT_ADDR + 0x180000CC0UL) #define APECS_MEM_B7TRA (IDENT_ADDR + 0x180000CE0UL) #define APECS_MEM_B8TRA (IDENT_ADDR + 0x180000D00UL) /* Bank x Timing Register B */ #define APECS_MEM_B0TRB (IDENT_ADDR + 0x180000E00UL) #define APECS_MEM_B1TRB (IDENT_ADDR + 0x180000E20UL) #define APECS_MEM_B2TRB (IDENT_ADDR + 0x180000E40UL) #define APECS_MEM_B3TRB (IDENT_ADDR + 0x180000E60UL) #define APECS_MEM_B4TRB (IDENT_ADDR + 0x180000E80UL) #define APECS_MEM_B5TRB (IDENT_ADDR + 0x180000EA0UL) #define APECS_MEM_B6TRB (IDENT_ADDR + 0x180000EC0UL) #define APECS_MEM_B7TRB (IDENT_ADDR + 0x180000EE0UL) #define APECS_MEM_B8TRB (IDENT_ADDR + 0x180000F00UL) /* * Memory spaces: */ #define APECS_IACK_SC (IDENT_ADDR + 0x1b0000000UL) #define APECS_CONF (IDENT_ADDR + 0x1e0000000UL) #define APECS_IO (IDENT_ADDR + 0x1c0000000UL) #define APECS_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) #define APECS_DENSE_MEM (IDENT_ADDR + 0x300000000UL) /* * Bit definitions for I/O Controller status register 0: */ #define APECS_IOC_STAT0_CMD 0xf #define APECS_IOC_STAT0_ERR (1<<4) #define APECS_IOC_STAT0_LOST (1<<5) #define APECS_IOC_STAT0_THIT (1<<6) #define APECS_IOC_STAT0_TREF (1<<7) #define APECS_IOC_STAT0_CODE_SHIFT 8 #define APECS_IOC_STAT0_CODE_MASK 0x7 #define APECS_IOC_STAT0_P_NBR_SHIFT 13 #define APECS_IOC_STAT0_P_NBR_MASK 0x7ffff #define HAE_ADDRESS APECS_IOC_HAXR1 #ifdef __KERNEL__ /* * Translate physical memory address as seen on (PCI) bus into * a kernel virtual address and vv. */ /* NOTE: we fudge the window 1 maximum as 48Mb instead of 64Mb, to prevent virt_to_bus() from returning an address in the first window, for a data area that goes beyond the 64Mb first DMA window. Sigh... This MUST match with <asm/dma.h> MAX_DMA_ADDRESS for consistency, but we can't just use that here, because of header file looping... :-( */ extern inline unsigned long virt_to_bus(void * address) { unsigned long paddr = virt_to_phys(address); #ifdef CONFIG_ALPHA_XL if (paddr < APECS_XL_DMA_WIN1_SIZE_PARANOID) return paddr + APECS_XL_DMA_WIN1_BASE; else return paddr + APECS_XL_DMA_WIN2_BASE; /* win 2 xlates to 0 also */ #else /* CONFIG_ALPHA_XL */ return paddr + APECS_DMA_WIN_BASE; #endif /* CONFIG_ALPHA_XL */ } extern inline void * bus_to_virt(unsigned long address) { /* * This check is a sanity check but also ensures that bus * address 0 maps to virtual address 0 which is useful to * detect null "pointers" (the NCR driver is much simpler if * NULL pointers are preserved). */ #ifdef CONFIG_ALPHA_XL if (address < APECS_XL_DMA_WIN1_BASE) return 0; else if (address < (APECS_XL_DMA_WIN1_BASE + APECS_XL_DMA_WIN1_SIZE)) return phys_to_virt(address - APECS_XL_DMA_WIN1_BASE); else /* should be more checking here, maybe? */ return phys_to_virt(address - APECS_XL_DMA_WIN2_BASE); #else /* CONFIG_ALPHA_XL */ if (address < APECS_DMA_WIN_BASE) return 0; return phys_to_virt(address - APECS_DMA_WIN_BASE); #endif /* CONFIG_ALPHA_XL */ } /* * I/O functions: * * Unlike Jensen, the APECS machines have no concept of local * I/O---everything goes over the PCI bus. * * There is plenty room for optimization here. In particular, * the Alpha's insb/insw/extb/extw should be useful in moving * data to/from the right byte-lanes. */ #define vuip volatile unsigned int * extern inline unsigned int __inb(unsigned long addr) { long result = *(vuip) ((addr << 5) + APECS_IO + 0x00); result >>= (addr & 3) * 8; return 0xffUL & result; } extern inline void __outb(unsigned char b, unsigned long addr) { unsigned int w; asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); *(vuip) ((addr << 5) + APECS_IO + 0x00) = w; mb(); } extern inline unsigned int __inw(unsigned long addr) { long result = *(vuip) ((addr << 5) + APECS_IO + 0x08); result >>= (addr & 3) * 8; return 0xffffUL & result; } extern inline void __outw(unsigned short b, unsigned long addr) { unsigned int w; asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); *(vuip) ((addr << 5) + APECS_IO + 0x08) = w; mb(); } extern inline unsigned int __inl(unsigned long addr) { return *(vuip) ((addr << 5) + APECS_IO + 0x18); } extern inline void __outl(unsigned int b, unsigned long addr) { *(vuip) ((addr << 5) + APECS_IO + 0x18) = b; mb(); } /* * Memory functions. 64-bit and 32-bit accesses are done through * dense memory space, everything else through sparse space. */ extern inline unsigned long __readb(unsigned long addr) { unsigned long result, shift, msb; shift = (addr & 0x3) * 8; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; if (msb != hae.cache) { set_hae(msb); } } result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00); result >>= shift; return 0xffUL & result; } extern inline unsigned long __readw(unsigned long addr) { unsigned long result, shift, msb; shift = (addr & 0x3) * 8; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; if (msb != hae.cache) { set_hae(msb); } } result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08); result >>= shift; return 0xffffUL & result; } extern inline unsigned long __readl(unsigned long addr) { return *(vuip) (addr + APECS_DENSE_MEM); } extern inline void __writeb(unsigned char b, unsigned long addr) { unsigned long msb; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; if (msb != hae.cache) { set_hae(msb); } } *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00) = b * 0x01010101; } extern inline void __writew(unsigned short b, unsigned long addr) { unsigned long msb; if (addr >= (1UL << 24)) { msb = addr & 0xf8000000; addr -= msb; if (msb != hae.cache) { set_hae(msb); } } *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08) = b * 0x00010001; } extern inline void __writel(unsigned int b, unsigned long addr) { *(vuip) (addr + APECS_DENSE_MEM) = b; } #define inb(port) \ (__builtin_constant_p((port))?__inb(port):_inb(port)) #define outb(x, port) \ (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) #define readl(a) __readl((unsigned long)(a)) #define writel(v,a) __writel((v),(unsigned long)(a)) #undef vuip extern unsigned long apecs_init (unsigned long mem_start, unsigned long mem_end); #endif /* __KERNEL__ */ /* * Data structure for handling APECS machine checks: */ #ifdef CONFIG_ALPHA_MIKASA struct el_apecs_sysdata_mcheck { unsigned long coma_gcr; unsigned long coma_edsr; unsigned long coma_ter; unsigned long coma_elar; unsigned long coma_ehar; unsigned long coma_ldlr; unsigned long coma_ldhr; unsigned long coma_base0; unsigned long coma_base1; unsigned long coma_base2; unsigned long coma_base3; unsigned long coma_cnfg0; unsigned long coma_cnfg1; unsigned long coma_cnfg2; unsigned long coma_cnfg3; unsigned long epic_dcsr; unsigned long epic_pear; unsigned long epic_sear; unsigned long epic_tbr1; unsigned long epic_tbr2; unsigned long epic_pbr1; unsigned long epic_pbr2; unsigned long epic_pmr1; unsigned long epic_pmr2; unsigned long epic_harx1; unsigned long epic_harx2; unsigned long epic_pmlt; unsigned long epic_tag0; unsigned long epic_tag1; unsigned long epic_tag2; unsigned long epic_tag3; unsigned long epic_tag4; unsigned long epic_tag5; unsigned long epic_tag6; unsigned long epic_tag7; unsigned long epic_data0; unsigned long epic_data1; unsigned long epic_data2; unsigned long epic_data3; unsigned long epic_data4; unsigned long epic_data5; unsigned long epic_data6; unsigned long epic_data7; unsigned long pceb_vid; unsigned long pceb_did; unsigned long pceb_revision; unsigned long pceb_command; unsigned long pceb_status; unsigned long pceb_latency; unsigned long pceb_control; unsigned long pceb_arbcon; unsigned long pceb_arbpri; unsigned long esc_id; unsigned long esc_revision; unsigned long esc_int0; unsigned long esc_int1; unsigned long esc_elcr0; unsigned long esc_elcr1; unsigned long esc_last_eisa; unsigned long esc_nmi_stat; unsigned long pci_ir; unsigned long pci_imr; unsigned long svr_mgr; }; #else /* CONFIG_ALPHA_MIKASA */ /* this for the normal APECS machines */ struct el_apecs_sysdata_mcheck { unsigned long coma_gcr; unsigned long coma_edsr; unsigned long coma_ter; unsigned long coma_elar; unsigned long coma_ehar; unsigned long coma_ldlr; unsigned long coma_ldhr; unsigned long coma_base0; unsigned long coma_base1; unsigned long coma_base2; unsigned long coma_cnfg0; unsigned long coma_cnfg1; unsigned long coma_cnfg2; unsigned long epic_dcsr; unsigned long epic_pear; unsigned long epic_sear; unsigned long epic_tbr1; unsigned long epic_tbr2; unsigned long epic_pbr1; unsigned long epic_pbr2; unsigned long epic_pmr1; unsigned long epic_pmr2; unsigned long epic_harx1; unsigned long epic_harx2; unsigned long epic_pmlt; unsigned long epic_tag0; unsigned long epic_tag1; unsigned long epic_tag2; unsigned long epic_tag3; unsigned long epic_tag4; unsigned long epic_tag5; unsigned long epic_tag6; unsigned long epic_tag7; unsigned long epic_data0; unsigned long epic_data1; unsigned long epic_data2; unsigned long epic_data3; unsigned long epic_data4; unsigned long epic_data5; unsigned long epic_data6; unsigned long epic_data7; }; #endif /* CONFIG_ALPHA_MIKASA */ struct el_procdata { unsigned long paltemp[32]; /* PAL TEMP REGS. */ /* EV4-specific fields */ unsigned long exc_addr; /* Address of excepting instruction. */ unsigned long exc_sum; /* Summary of arithmetic traps. */ unsigned long exc_mask; /* Exception mask (from exc_sum). */ unsigned long iccsr; /* IBox hardware enables. */ unsigned long pal_base; /* Base address for PALcode. */ unsigned long hier; /* Hardware Interrupt Enable. */ unsigned long hirr; /* Hardware Interrupt Request. */ unsigned long csr; /* D-stream fault info. */ unsigned long dc_stat; /* D-cache status (ECC/Parity Err). */ unsigned long dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ unsigned long abox_ctl; /* ABox Control Register. */ unsigned long biu_stat; /* BIU Status. */ unsigned long biu_addr; /* BUI Address. */ unsigned long biu_ctl; /* BIU Control. */ unsigned long fill_syndrome;/* For correcting ECC errors. */ unsigned long fill_addr; /* Cache block which was being read */ unsigned long va; /* Effective VA of fault or miss. */ unsigned long bc_tag; /* Backup Cache Tag Probe Results.*/ }; #define RTC_PORT(x) (0x70 + (x)) #define RTC_ADDR(x) (0x80 | (x)) #define RTC_ALWAYS_BCD 0 #endif /* __ALPHA_APECS__H__ */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/atomic.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/atomic.h?rev=1.1&content-type=text/x-cvsweb-markup Index: atomic.h =================================================================== #ifndef __ARCH_ALPHA_ATOMIC__ #define __ARCH_ALPHA_ATOMIC__ /* * Atomic operations that C can't guarantee us. Useful for * resource counting etc... * * But use these as seldom as possible since they are much more slower * than regular operations. */ /* * Make sure gcc doesn't try to be clever and move things around * on us. We need to use _exactly_ the address the user gave us, * not some alias that contains the same information. */ #define __atomic_fool_gcc(x) (*(struct { int a[100]; } *)x) typedef int atomic_t; extern __inline__ void atomic_add(atomic_t i, atomic_t * v) { unsigned long temp; __asm__ __volatile__( "\n1:\t" "ldl_l %0,%1\n\t" "addl %0,%2,%0\n\t" "stl_c %0,%1\n\t" "beq %0,1b\n" "2:" :"=&r" (temp), "=m" (__atomic_fool_gcc(v)) :"Ir" (i), "m" (__atomic_fool_gcc(v))); } extern __inline__ void atomic_sub(atomic_t i, atomic_t * v) { unsigned long temp; __asm__ __volatile__( "\n1:\t" "ldl_l %0,%1\n\t" "subl %0,%2,%0\n\t" "stl_c %0,%1\n\t" "beq %0,1b\n" "2:" :"=&r" (temp), "=m" (__atomic_fool_gcc(v)) :"Ir" (i), "m" (__atomic_fool_gcc(v))); } /* * Same as above, but return the result value */ extern __inline__ long atomic_add_return(atomic_t i, atomic_t * v) { long temp, result; __asm__ __volatile__( "\n1:\t" "ldl_l %0,%1\n\t" "addl %0,%3,%0\n\t" "bis %0,%0,%2\n\t" "stl_c %0,%1\n\t" "beq %0,1b\n" "2:" :"=&r" (temp), "=m" (__atomic_fool_gcc(v)), "=&r" (result) :"Ir" (i), "m" (__atomic_fool_gcc(v))); return result; } extern __inline__ long atomic_sub_return(atomic_t i, atomic_t * v) { long temp, result; __asm__ __volatile__( "\n1:\t" "ldl_l %0,%1\n\t" "subl %0,%3,%0\n\t" "bis %0,%0,%2\n\t" "stl_c %0,%1\n\t" "beq %0,1b\n" "2:" :"=&r" (temp), "=m" (__atomic_fool_gcc(v)), "=&r" (result) :"Ir" (i), "m" (__atomic_fool_gcc(v))); return result; } #define atomic_dec_return(v) atomic_sub_return(1,(v)) #define atomic_inc_return(v) atomic_add_return(1,(v)) #define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) #define atomic_inc(v) atomic_add(1,(v)) #define atomic_dec(v) atomic_sub(1,(v)) #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/bitops.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/bitops.h?rev=1.1&content-type=text/x-cvsweb-markup Index: bitops.h =================================================================== #ifndef _ALPHA_BITOPS_H #define _ALPHA_BITOPS_H /* * Copyright 1994, Linus Torvalds. */ /* * These have to be done with inline assembly: that way the bit-setting * is guaranteed to be atomic. All bit operations return 0 if the bit * was cleared before the operation and != 0 if it was not. * * bit 0 is the LSB of addr; bit 64 is the LSB of (addr+1). */ extern __inline__ unsigned long set_bit(unsigned long nr, void * addr) { unsigned long oldbit; unsigned long temp; unsigned int * m = ((unsigned int *) addr) + (nr >> 5); __asm__ __volatile__( "\n1:\t" "ldl_l %0,%1\n\t" "and %0,%3,%2\n\t" "bne %2,2f\n\t" "xor %0,%3,%0\n\t" "stl_c %0,%1\n\t" "beq %0,1b\n" "2:" :"=&r" (temp), "=m" (*m), "=&r" (oldbit) :"Ir" (1UL << (nr & 31)), "m" (*m)); return oldbit != 0; } extern __inline__ unsigned long clear_bit(unsigned long nr, void * addr) { unsigned long oldbit; unsigned long temp; unsigned int * m = ((unsigned int *) addr) + (nr >> 5); __asm__ __volatile__( "\n1:\t" "ldl_l %0,%1\n\t" "and %0,%3,%2\n\t" "beq %2,2f\n\t" "xor %0,%3,%0\n\t" "stl_c %0,%1\n\t" "beq %0,1b\n" "2:" :"=&r" (temp), "=m" (*m), "=&r" (oldbit) :"Ir" (1UL << (nr & 31)), "m" (*m)); return oldbit != 0; } extern __inline__ unsigned long change_bit(unsigned long nr, void * addr) { unsigned long oldbit; unsigned long temp; unsigned int * m = ((unsigned int *) addr) + (nr >> 5); __asm__ __volatile__( "\n1:\t" "ldl_l %0,%1\n\t" "and %0,%3,%2\n\t" "xor %0,%3,%0\n\t" "stl_c %0,%1\n\t" "beq %0,1b\n" :"=&r" (temp), "=m" (*m), "=&r" (oldbit) :"Ir" (1UL << (nr & 31)), "m" (*m)); return oldbit != 0; } extern __inline__ unsigned long test_bit(int nr, const void * addr) { return 1UL & (((const int *) addr)[nr >> 5] >> (nr & 31)); } /* * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. * * Do a binary search on the bits. Due to the nature of large * constants on the alpha, it is worthwhile to split the search. */ extern inline unsigned long ffz_b(unsigned long x) { unsigned long sum = 0; x = ~x & -~x; /* set first 0 bit, clear others */ if (x & 0xF0) sum += 4; if (x & 0xCC) sum += 2; if (x & 0xAA) sum += 1; return sum; } extern inline unsigned long ffz(unsigned long word) { unsigned long bits, qofs, bofs; __asm__("cmpbge %1,%2,%0" : "=r"(bits) : "r"(word), "r"(~0UL)); qofs = ffz_b(bits); __asm__("extbl %1,%2,%0" : "=r"(bits) : "r"(word), "r"(qofs)); bofs = ffz_b(bits); return qofs*8 + bofs; } /* * Find next zero bit in a bitmap reasonably efficiently.. */ extern inline unsigned long find_next_zero_bit(void * addr, unsigned long size, unsigned long offset) { unsigned long * p = ((unsigned long *) addr) + (offset >> 6); unsigned long result = offset & ~63UL; unsigned long tmp; if (offset >= size) return size; size -= result; offset &= 63UL; if (offset) { tmp = *(p++); tmp |= ~0UL >> (64-offset); if (size < 64) goto found_first; if (~tmp) goto found_middle; size -= 64; result += 64; } while (size & ~63UL) { if (~(tmp = *(p++))) goto found_middle; result += 64; size -= 64; } if (!size) return result; tmp = *p; found_first: tmp |= ~0UL << size; found_middle: return result + ffz(tmp); } /* * The optimizer actually does good code for this case.. */ #define find_first_zero_bit(addr, size) \ find_next_zero_bit((addr), (size), 0) #endif /* _ALPHA_BITOPS_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/bugs.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/bugs.h?rev=1.1&content-type=text/x-cvsweb-markup Index: bugs.h =================================================================== /* * include/asm-alpha/bugs.h * * Copyright (C) 1994 Linus Torvalds */ /* * This is included by init/main.c to check for architecture-dependent bugs. * * Needs: * void check_bugs(void); */ /* * I don't know of any alpha bugs yet.. Nice chip */ static void check_bugs(void) { } 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/byteorder.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/byteorder.h?rev=1.1&content-type=text/x-cvsweb-markup Index: byteorder.h =================================================================== #ifndef _ALPHA_BYTEORDER_H #define _ALPHA_BYTEORDER_H #undef ntohl #undef ntohs #undef htonl #undef htons #ifndef __LITTLE_ENDIAN #define __LITTLE_ENDIAN #endif #ifndef __LITTLE_ENDIAN_BITFIELD #define __LITTLE_ENDIAN_BITFIELD #endif extern unsigned long int ntohl(unsigned long int); extern unsigned short int ntohs(unsigned short int); extern unsigned long int htonl(unsigned long int); extern unsigned short int htons(unsigned short int); extern unsigned long int __ntohl(unsigned long int); extern unsigned short int __ntohs(unsigned short int); #ifdef __GNUC__ extern unsigned long int __constant_ntohl(unsigned long int); extern unsigned short int __constant_ntohs(unsigned short int); /* * The constant and non-constant versions here are the same. * Maybe I'll come up with an alpha-optimized routine for the * non-constant ones (the constant ones don't need it: gcc * will optimize it to the correct constant) */ extern __inline__ unsigned long int __ntohl(unsigned long int x) { unsigned long int res, t1, t2; __asm__( "# bswap input: %0 (aabbccdd)\n\t" "# output: %0, used %1 %2\n\t" "extlh %0,5,%1 # %1 = dd000000\n\t" "zap %0,0xfd,%2 # %2 = 0000cc00\n\t" "sll %2,5,%2 # %2 = 00198000\n\t" "s8addq %2,%1,%1 # %1 = ddcc0000\n\t" "zap %0,0xfb,%2 # %2 = 00bb0000\n\t" "srl %2,8,%2 # %2 = 0000bb00\n\t" "extbl %0,3,%0 # %0 = 000000aa\n\t" "or %1,%0,%0 # %0 = ddcc00aa\n\t" "or %2,%0,%0 # %0 = ddccbbaa\n" : "r="(res), "r="(t1), "r="(t2) : "0" (x & 0xffffffffUL)); return res; } #define __constant_ntohl(x) \ ((unsigned long int)((((x) & 0x000000ffUL) << 24) | \ (((x) & 0x0000ff00UL) << 8) | \ (((x) & 0x00ff0000UL) >> 8) | \ (((x) & 0xff000000UL) >> 24))) extern __inline__ unsigned short int __ntohs(unsigned short int x) { unsigned long int res, t1; __asm__( "# v0 is result; swap in-place.\n\t" "bis %2,%2,%0 # v0 = aabb\n\t" "extwh %0,7,%1 # t1 = bb00\n\t" "extbl %0,1,%0 # v0 = 00aa\n\t" "bis %0,%1,%0 # v0 = bbaa\n" : "r="(res), "r="(t1) : "r"(x)); return res; } #define __constant_ntohs(x) \ ((unsigned short int)((((unsigned short int)(x) & 0x00ff) << 8) | \ (((unsigned short int)(x) & 0xff00) >> 8))) #define __htonl(x) __ntohl(x) #define __htons(x) __ntohs(x) #define __constant_htonl(x) __constant_ntohl(x) #define __constant_htons(x) __constant_ntohs(x) #ifdef __OPTIMIZE__ # define ntohl(x) \ (__builtin_constant_p((long)(x)) ? \ __constant_ntohl((x)) : \ __ntohl((x))) # define ntohs(x) \ (__builtin_constant_p((short)(x)) ? \ __constant_ntohs((x)) : \ __ntohs((x))) # define htonl(x) \ (__builtin_constant_p((long)(x)) ? \ __constant_htonl((x)) : \ __htonl((x))) # define htons(x) \ (__builtin_constant_p((short)(x)) ? \ __constant_htons((x)) : \ __htons((x))) #endif /* __OPTIMIZE__ */ #endif /* __GNUC__ */ #endif /* _ALPHA_BYTEORDER_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/checksum.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/checksum.h?rev=1.1&content-type=text/x-cvsweb-markup Index: checksum.h =================================================================== #ifndef _ALPHA_CHECKSUM_H #define _ALPHA_CHECKSUM_H /* * This is a version of ip_compute_csum() optimized for IP headers, * which always checksum on 4 octet boundaries. */ extern unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl); /* * computes the checksum of the TCP/UDP pseudo-header * returns a 16-bit checksum, already complemented */ extern unsigned short int csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len, unsigned short proto, unsigned int sum); /* * computes the checksum of a memory block at buff, length len, * and adds in "sum" (32-bit) * * returns a 32-bit number suitable for feeding into itself * or csum_tcpudp_magic * * this function must be called with even lengths, except * for the last fragment, which may be odd * * it's best to have buff aligned on a 32-bit boundary */ extern unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum); /* * the same as csum_partial, but copies from src while it * checksums * * here even more important to align src and dst on a 32-bit (or even * better 64-bit) boundary */ unsigned int csum_partial_copy( const char *src, char *dst, int len, int sum); /* * the same as csum_partial, but copies from user space (but on the alpha * we have just one address space, so this is identical to the above) */ #define csum_partial_copy_fromuser csum_partial_copy /* * this routine is used for miscellaneous IP-like checksums, mainly * in icmp.c */ extern unsigned short ip_compute_csum(unsigned char * buff, int len); /* * Fold a partial checksum without adding pseudo headers */ static inline unsigned short csum_fold(unsigned int sum) { sum = (sum & 0xffff) + (sum >> 16); sum = (sum & 0xffff) + (sum >> 16); return ~sum; } #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/cia.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/cia.h?rev=1.1&content-type=text/x-cvsweb-markup Index: cia.h =================================================================== #ifndef __ALPHA_CIA__H__ #define __ALPHA_CIA__H__ #include <linux/config.h> #include <linux/types.h> /* * CIA is the internal name for the 2117x chipset which provides * memory controller and PCI access for the 21164 chip based systems. * * This file is based on: * * DECchip 21171 Core Logic Chipset * Technical Reference Manual * * EC-QE18B-TE * * david.rusling@r... Initial Version. * */ /*------------------------------------------------------------------------** ** ** ** EB164 I/O procedures ** ** ** ** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers ** ** inportbxt: 8 bits only ** ** inport: alias of inportw ** ** outport: alias of outportw ** ** ** ** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers ** ** inmembxt: 8 bits only ** ** inmem: alias of inmemw ** ** outmem: alias of outmemw ** ** ** **------------------------------------------------------------------------*/ /* CIA ADDRESS BIT DEFINITIONS * * 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0| * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | \_/ \_/ * | | | * +-- IO space, not cached. Byte Enable --+ | * Transfer Length --+ * * * * Byte Transfer * Enable Length Transfer Byte Address * adr<6:5> adr<4:3> Length Enable Adder * --------------------------------------------- * 00 00 Byte 1110 0x000 * 01 00 Byte 1101 0x020 * 10 00 Byte 1011 0x040 * 11 00 Byte 0111 0x060 * * 00 01 Word 1100 0x008 * 01 01 Word 1001 0x028 <= Not supported in this code. * 10 01 Word 0011 0x048 * * 00 10 Tribyte 1000 0x010 * 01 10 Tribyte 0001 0x030 * * 10 11 Longword 0000 0x058 * * Note that byte enables are asserted low. * */ #define BYTE_ENABLE_SHIFT 5 #define TRANSFER_LENGTH_SHIFT 3 #define MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */ #define MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */ #define MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */ #ifdef CONFIG_ALPHA_SRM_SETUP /* if we are using the SRM PCI setup, we'll need to use variables instead */ #define CIA_DMA_WIN_BASE_DEFAULT (1024*1024*1024) #define CIA_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) extern unsigned int CIA_DMA_WIN_BASE; extern unsigned int CIA_DMA_WIN_SIZE; #else /* SRM_SETUP */ #define CIA_DMA_WIN_BASE (1024*1024*1024) #define CIA_DMA_WIN_SIZE (1024*1024*1024) #endif /* SRM_SETUP */ /* * 21171-CA Control and Status Registers (p4-1) */ #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL) #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL) #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL) #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL) #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL) #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL) #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL) #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL) /* * 21171-CA Diagnostic Registers (p4-2) */ #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL) #define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL) /* * 21171-CA Performance Monitor registers (p4-3) */ #define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL) #define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL) /* * 21171-CA Error registers (p4-3) */ #define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL) #define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL) #define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL) #define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL) #define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL) #define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL) #define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL) #define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL) #define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL) #define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL) #define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL) /* * 2117A-CA PCI Address Translation Registers. */ #define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL) #define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL) #define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL) #define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL) #define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL) #define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL) #define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL) #define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL) #define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL) #define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL) #define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL) #define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL) #define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL) /* * 21171-CA System configuration registers (p4-3) */ #define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL) #define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL) #define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL) #define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL) #define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL) #define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL) #define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL) #define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL) #define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL) #define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL) #define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL) #define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL) /* * Memory spaces: */ #define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL) #define CIA_CONF (IDENT_ADDR + 0x8700000000UL) #define CIA_IO (IDENT_ADDR + 0x8580000000UL) #define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL) #define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL) #define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL) #define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL) /* * ALCOR's GRU ASIC registers */ #define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL) #define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL) #define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL) #define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL) #define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL) #define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL) #define GRU_SCR (IDENT_ADDR + 0x8780000300UL) #define GRU_LED (IDENT_ADDR + 0x8780000800UL) #define GRU_RESET (IDENT_ADDR + 0x8780000900UL) #if defined(CONFIG_ALPHA_ALCOR) #define GRU_INT_REQ_BITS 0x800fffffUL #elif defined(CONFIG_ALPHA_XLT) #define GRU_INT_REQ_BITS 0x80003fffUL #else #define GRU_INT_REQ_BITS 0xffffffffUL #endif /* * Bit definitions for I/O Controller status register 0: */ #define CIA_IOC_STAT0_CMD 0xf #define CIA_IOC_STAT0_ERR (1<<4) #define CIA_IOC_STAT0_LOST (1<<5) #define CIA_IOC_STAT0_THIT (1<<6) #define CIA_IOC_STAT0_TREF (1<<7) #define CIA_IOC_STAT0_CODE_SHIFT 8 #define CIA_IOC_STAT0_CODE_MASK 0x7 #define CIA_IOC_STAT0_P_NBR_SHIFT 13 #define CIA_IOC_STAT0_P_NBR_MASK 0x7ffff #define HAE_ADDRESS CIA_IOC_HAE_MEM #ifdef __KERNEL__ /* * Translate physical memory address as seen on (PCI) bus into * a kernel virtual address and vv. */ extern inline unsigned long virt_to_bus(void * address) { return virt_to_phys(address) + CIA_DMA_WIN_BASE; } extern inline void * bus_to_virt(unsigned long address) { return phys_to_virt(address - CIA_DMA_WIN_BASE); } /* * I/O functions: * * CIA (the 2117x PCI/memory support chipset for the EV5 (21164) * series of processors uses a sparse address mapping scheme to * get at PCI memory and I/O. */ #define vuip volatile unsigned int * extern inline unsigned int __inb(unsigned long addr) { long result = *(vuip) ((addr << 5) + CIA_IO + 0x00); result >>= (addr & 3) * 8; return 0xffUL & result; } extern inline void __outb(unsigned char b, unsigned long addr) { unsigned int w; asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); *(vuip) ((addr << 5) + CIA_IO + 0x00) = w; mb(); } extern inline unsigned int __inw(unsigned long addr) { long result = *(vuip) ((addr << 5) + CIA_IO + 0x08); result >>= (addr & 3) * 8; return 0xffffUL & result; } extern inline void __outw(unsigned short b, unsigned long addr) { unsigned int w; asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); *(vuip) ((addr << 5) + CIA_IO + 0x08) = w; mb(); } extern inline unsigned int __inl(unsigned long addr) { return *(vuip) ((addr << 5) + CIA_IO + 0x18); } extern inline void __outl(unsigned int b, unsigned long addr) { *(vuip) ((addr << 5) + CIA_IO + 0x18) = b; mb(); } /* * Memory functions. 64-bit and 32-bit accesses are done through * dense memory space, everything else through sparse space. * * For reading and writing 8 and 16 bit quantities we need to * go through one of the three sparse address mapping regions * and use the HAE_MEM CSR to provide some bits of the address. * The following few routines use only sparse address region 1 * which gives 1Gbyte of accessible space which relates exactly * to the amount of PCI memory mapping *into* system address space. * See p 6-17 of the specification but it looks something like this: * * 21164 Address: * * 3 2 1 * 9876543210987654321098765432109876543210 * 1ZZZZ0.PCI.QW.Address............BBLL * * ZZ = SBZ * BB = Byte offset * LL = Transfer length * * PCI Address: * * 3 2 1 * 10987654321098765432109876543210 * HHH....PCI.QW.Address........ 00 * * HHH = 31:29 HAE_MEM CSR * */ #ifdef CONFIG_ALPHA_SRM_SETUP extern unsigned long cia_sm_base_r1, cia_sm_base_r2, cia_sm_base_r3; extern inline unsigned long __readb(unsigned long addr) { unsigned long result, shift, work; if ((addr >= cia_sm_base_r1) && (addr <= (cia_sm_base_r1 + MEM_R1_MASK))) work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00); else if ((addr >= cia_sm_base_r2) && (addr <= (cia_sm_base_r2 + MEM_R2_MASK))) work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00); else if ((addr >= cia_sm_base_r3) && (addr <= (cia_sm_base_r3 + MEM_R3_MASK))) work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00); else { #if 0 printk("__readb: address 0x%lx not covered by HAE\n", addr); #endif return 0x0ffUL; } shift = (addr & 0x3) << 3; result = *(vuip) work; result >>= shift; return 0x0ffUL & result; } extern inline unsigned long __readw(unsigned long addr) { unsigned long result, shift, work; if ((addr >= cia_sm_base_r1) && (addr <= (cia_sm_base_r1 + MEM_R1_MASK))) work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x08); else if ((addr >= cia_sm_base_r2) && (addr <= (cia_sm_base_r2 + MEM_R2_MASK))) work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x08); else if ((addr >= cia_sm_base_r3) && (addr <= (cia_sm_base_r3 + MEM_R3_MASK))) work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x08); else { #if 0 printk("__readw: address 0x%lx not covered by HAE\n", addr); #endif return 0x0ffUL; } shift = (addr & 0x3) << 3; result = *(vuip) work; result >>= shift; return 0x0ffffUL & result; } extern inline void __writeb(unsigned char b, unsigned long addr) { unsigned long work; if ((addr >= cia_sm_base_r1) && (addr <= (cia_sm_base_r1 + MEM_R1_MASK))) work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00); else if ((addr >= cia_sm_base_r2) && (addr <= (cia_sm_base_r2 + MEM_R2_MASK))) work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00); else if ((addr >= cia_sm_base_r3) && (addr <= (cia_sm_base_r3 + MEM_R3_MASK))) work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00); else { #if 0 printk("__writeb: address 0x%lx not covered by HAE\n", addr); #endif return; } *(vuip) work = b * 0x01010101; } extern inline void __writew(unsigned short b, unsigned long addr) { unsigned long work; if ((addr >= cia_sm_base_r1) && (addr <= (cia_sm_base_r1 + MEM_R1_MASK))) work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00); else if ((addr >= cia_sm_base_r2) && (addr <= (cia_sm_base_r2 + MEM_R2_MASK))) work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00); else if ((addr >= cia_sm_base_r3) && (addr <= (cia_sm_base_r3 + MEM_R3_MASK))) work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00); else { #if 0 printk("__writew: address 0x%lx not covered by HAE\n", addr); #endif return; } *(vuip) work = b * 0x00010001; } #else /* SRM_SETUP */ extern inline unsigned long __readb(unsigned long addr) { unsigned long result, shift, msb; shift = (addr & 0x3) * 8 ; msb = addr & 0xE0000000 ; addr &= MEM_R1_MASK ; if (msb != hae.cache) { set_hae(msb); } result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) ; result >>= shift; return 0xffUL & result; } extern inline unsigned long __readw(unsigned long addr) { unsigned long result, shift, msb; shift = (addr & 0x3) * 8; msb = addr & 0xE0000000 ; addr &= MEM_R1_MASK ; if (msb != hae.cache) { set_hae(msb); } result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08); result >>= shift; return 0xffffUL & result; } extern inline void __writeb(unsigned char b, unsigned long addr) { unsigned long msb ; msb = addr & 0xE0000000 ; addr &= MEM_R1_MASK ; if (msb != hae.cache) { set_hae(msb); } *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = b * 0x01010101; } extern inline void __writew(unsigned short b, unsigned long addr) { unsigned long msb ; msb = addr & 0xE0000000 ; addr &= MEM_R1_MASK ; if (msb != hae.cache) { set_hae(msb); } *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = b * 0x00010001; } #endif /* SRM_SETUP */ extern inline unsigned long __readl(unsigned long addr) { return *(vuip) (addr + CIA_DENSE_MEM); } extern inline void __writel(unsigned int b, unsigned long addr) { *(vuip) (addr + CIA_DENSE_MEM) = b; } #define inb(port) \ (__builtin_constant_p((port))?__inb(port):_inb(port)) #define outb(x, port) \ (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) #define readl(a) __readl((unsigned long)(a)) #define writel(v,a) __writel((v),(unsigned long)(a)) #undef vuip extern unsigned long cia_init (unsigned long mem_start, unsigned long mem_end); #endif /* __KERNEL__ */ /* * Data structure for handling CIA machine checks: */ /* ev5-specific info: */ struct el_procdata { unsigned long shadow[8]; /* PALmode shadow registers */ unsigned long paltemp[24]; /* PAL temporary registers */ /* EV5-specific fields */ unsigned long exc_addr; /* Address of excepting instruction. */ unsigned long exc_sum; /* Summary of arithmetic traps. */ unsigned long exc_mask; /* Exception mask (from exc_sum). */ unsigned long exc_base; /* PALbase at time of exception. */ unsigned long isr; /* Interrupt summary register. */ unsigned long icsr; /* Ibox control register. */ unsigned long ic_perr_stat; unsigned long dc_perr_stat; unsigned long va; /* Effective VA of fault or miss. */ unsigned long mm_stat; unsigned long sc_addr; unsigned long sc_stat; unsigned long bc_tag_addr; unsigned long ei_addr; unsigned long fill_syn; unsigned long ei_stat; unsigned long ld_lock; }; /* system-specific info: */ struct el_CIA_sysdata_mcheck { unsigned long coma_gcr; unsigned long coma_edsr; unsigned long coma_ter; unsigned long coma_elar; unsigned long coma_ehar; unsigned long coma_ldlr; unsigned long coma_ldhr; unsigned long coma_base0; unsigned long coma_base1; unsigned long coma_base2; unsigned long coma_cnfg0; unsigned long coma_cnfg1; unsigned long coma_cnfg2; unsigned long epic_dcsr; unsigned long epic_pear; unsigned long epic_sear; unsigned long epic_tbr1; unsigned long epic_tbr2; unsigned long epic_pbr1; unsigned long epic_pbr2; unsigned long epic_pmr1; unsigned long epic_pmr2; unsigned long epic_harx1; unsigned long epic_harx2; unsigned long epic_pmlt; unsigned long epic_tag0; unsigned long epic_tag1; unsigned long epic_tag2; unsigned long epic_tag3; unsigned long epic_tag4; unsigned long epic_tag5; unsigned long epic_tag6; unsigned long epic_tag7; unsigned long epic_data0; unsigned long epic_data1; unsigned long epic_data2; unsigned long epic_data3; unsigned long epic_data4; unsigned long epic_data5; unsigned long epic_data6; unsigned long epic_data7; }; #define RTC_PORT(x) (0x70 + (x)) #define RTC_ADDR(x) (0x80 | (x)) #define RTC_ALWAYS_BCD 0 #endif /* __ALPHA_CIA__H__ */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/console.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/console.h?rev=1.1&content-type=text/x-cvsweb-markup Index: console.h =================================================================== #ifndef __AXP_CONSOLE_H #define __AXP_CONSOLE_H /* * Console callback routine numbers */ #define CCB_GETC 0x01 #define CCB_PUTS 0x02 #define CCB_RESET_TERM 0x03 #define CCB_SET_TERM_INT 0x04 #define CCB_SET_TERM_CTL 0x05 #define CCB_PROCESS_KEYCODE 0x06 #define CCB_OPEN 0x10 #define CCB_CLOSE 0x11 #define CCB_IOCTL 0x12 #define CCB_READ 0x13 #define CCB_WRITE 0x14 #define CCB_SET_ENV 0x20 #define CCB_RESET_ENV 0x21 #define CCB_GET_ENV 0x22 #define CCB_SAVE_ENV 0x23 /* * Environment variable numbers */ #define ENV_AUTO_ACTION 0x01 #define ENV_BOOT_DEV 0x02 #define ENV_BOOTDEF_DEV 0x03 #define ENV_BOOTED_DEV 0x04 #define ENV_BOOT_FILE 0x05 #define ENV_BOOTED_FILE 0x06 #define ENV_BOOT_OSFLAGS 0x07 #define ENV_BOOTED_OSFLAGS 0x08 #define ENV_BOOT_RESET 0x09 #define ENV_DUMP_DEV 0x0A #define ENV_ENABLE_AUDIT 0x0B #define ENV_LICENCE 0x0C #define ENV_CHAR_SET 0x0D #define ENV_LANGUAGE 0x0E #define ENV_TTY_DEV 0x0F extern unsigned long dispatch(unsigned long code, ...); #define puts(x,l) dispatch(CCB_PUTS,0,x,l) #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/delay.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/delay.h?rev=1.1&content-type=text/x-cvsweb-markup Index: delay.h =================================================================== #ifndef __ALPHA_DELAY_H #define __ALPHA_DELAY_H extern unsigned long loops_per_sec; /* * Copyright (C) 1993 Linus Torvalds * * Delay routines, using a pre-computed "loops_per_second" value. */ extern __inline__ void __delay(unsigned long loops) { __asm__ __volatile__(".align 3\n" "1:\tsubq %0,1,%0\n\t" "bge %0,1b": "=r" (loops) : "0" (loops)); } /* * division by multiplication: you don't have to worry about * loss of precision. * * Use only for very small delays ( < 1 msec). Should probably use a * lookup table, really, as the multiplications take much too long with * short delays. This is a "reasonable" implementation, though (and the * first constant multiplications gets optimized away if the delay is * a constant) */ extern __inline__ void udelay(unsigned long usecs) { usecs *= 0x000010c6f7a0b5edUL; /* 2**64 / 1000000 */ __asm__("umulh %1,%2,%0" :"=r" (usecs) :"r" (usecs),"r" (loops_per_sec)); __delay(usecs); } /* * 64-bit integers means we don't have to worry about overflow as * on some other architectures.. */ extern __inline__ unsigned long muldiv(unsigned long a, unsigned long b, unsigned long c) { return (a*b)/c; } #endif /* defined(__ALPHA_DELAY_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/dma.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/dma.h?rev=1.1&content-type=text/x-cvsweb-markup Index: dma.h =================================================================== /* * include/asm-alpha/dma.h * * This is essentially the same as the i386 DMA stuff, as the AlphaPCs * use ISA-compatible dma. The only extension is support for high-page * registers that allow to set the top 8 bits of a 32-bit DMA address. * This register should be written last when setting up a DMA address * as this will also enable DMA across 64 KB boundaries. */ /* $Id: dma.h,v 1.1 2005/12/20 11:20:29 jcastillo Exp $ * linux/include/asm/dma.h: Defines for using and allocating dma channels. * Written by Hennus Bergman, 1992. * High DMA channel support & info by Hannu Savolainen * and John Boyd, Nov. 1992. */ #ifndef _ASM_DMA_H #define _ASM_DMA_H #include <linux/config.h> #include <asm/io.h> /* need byte IO */ #define dma_outb outb #define dma_inb inb /* * NOTES about DMA transfers: * * controller 1: channels 0-3, byte operations, ports 00-1F * controller 2: channels 4-7, word operations, ports C0-DF * * - ALL registers are 8 bits only, regardless of transfer size * - channel 4 is not used - cascades 1 into 2. * - channels 0-3 are byte - addresses/counts are for physical bytes * - channels 5-7 are word - addresses/counts are for physical words * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries * - transfer count loaded to registers is 1 less than actual count * - controller 2 offsets are all even (2x offsets for controller 1) * - page registers for 5-7 don't use data bit 0, represent 128K pages * - page registers for 0-3 use bit 0, represent 64K pages * * DMA transfers are limited to the lower 16MB of _physical_ memory. * Note that addresses loaded into registers must be _physical_ addresses, * not logical addresses (which may differ if paging is active). * * Address mapping for channels 0-3: * * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) * | ... | | ... | | ... | * | ... | | ... | | ... | * | ... | | ... | | ... | * P7 ... P0 A7 ... A0 A7 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Address mapping for channels 5-7: * * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) * | ... | \ \ ... \ \ \ ... \ \ * | ... | \ \ ... \ \ \ ... \ (not used) * | ... | \ \ ... \ \ \ ... \ * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at * the hardware level, so odd-byte transfers aren't possible). * * Transfer count (_not # bytes_) is limited to 64K, represented as actual * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, * and up to 128K bytes may be transferred on channels 5-7 in one operation. * */ #define MAX_DMA_CHANNELS 8 #if defined(CONFIG_ALPHA_RUFFIAN) #define MAX_DMA_ADDRESS (0xfffffc0001000000UL) /* yup, 16Mb :-( */ #elif defined(CONFIG_ALPHA_XL) /* The maximum address that we can perform a DMA transfer to on Alpha XL, due to a hardware SIO (PCI<->ISA bus bridge) chip limitation, is 64MB. See <asm/apecs.h> for more info. */ /* NOTE: we must define the maximum as something less than 64Mb, to prevent virt_to_bus() from returning an address in the first window, for a data area that goes beyond the 64Mb first DMA window. Sigh... We MUST coordinate the maximum with <asm/apecs.h> for consistency. For now, this limit is set to 48Mb... */ #define MAX_DMA_ADDRESS (0xfffffc0003000000UL) #else /* * The maximum address that we can perform a DMA transfer to on * normal Alpha platforms */ #define MAX_DMA_ADDRESS (~0UL) #endif /* 8237 DMA controllers */ #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ /* DMA controller registers */ #define DMA1_CMD_REG 0x08 /* command register (w) */ #define DMA1_STAT_REG 0x08 /* status register (r) */ #define DMA1_REQ_REG 0x09 /* request register (w) */ #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ #define DMA1_MODE_REG 0x0B /* mode register (w) */ #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG) #define DMA2_CMD_REG 0xD0 /* command register (w) */ #define DMA2_STAT_REG 0xD0 /* status register (r) */ #define DMA2_REQ_REG 0xD2 /* request register (w) */ #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ #define DMA2_MODE_REG 0xD6 /* mode register (w) */ #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) #define DMA_ADDR_0 0x00 /* DMA address registers */ #define DMA_ADDR_1 0x02 #define DMA_ADDR_2 0x04 #define DMA_ADDR_3 0x06 #define DMA_ADDR_4 0xC0 #define DMA_ADDR_5 0xC4 #define DMA_ADDR_6 0xC8 #define DMA_ADDR_7 0xCC #define DMA_CNT_0 0x01 /* DMA count registers */ #define DMA_CNT_1 0x03 #define DMA_CNT_2 0x05 #define DMA_CNT_3 0x07 #define DMA_CNT_4 0xC2 #define DMA_CNT_5 0xC6 #define DMA_CNT_6 0xCA #define DMA_CNT_7 0xCE #define DMA_PAGE_0 0x87 /* DMA page registers */ #define DMA_PAGE_1 0x83 #define DMA_PAGE_2 0x81 #define DMA_PAGE_3 0x82 #define DMA_PAGE_5 0x8B #define DMA_PAGE_6 0x89 #define DMA_PAGE_7 0x8A #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0) #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1) #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2) #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3) #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4) #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5) #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6) #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7) #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ /* enable/disable a specific DMA channel */ static __inline__ void enable_dma(unsigned int dmanr) { if (dmanr<=3) dma_outb(dmanr, DMA1_MASK_REG); else dma_outb(dmanr & 3, DMA2_MASK_REG); } static __inline__ void disable_dma(unsigned int dmanr) { if (dmanr<=3) dma_outb(dmanr | 4, DMA1_MASK_REG); else dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); } /* Clear the 'DMA Pointer Flip Flop'. * Write 0 for LSB/MSB, 1 for MSB/LSB access. * Use this once to initialize the FF to a known state. * After that, keep track of it. :-) * --- In order to do that, the DMA routines below should --- * --- only be used while interrupts are disabled! --- */ static __inline__ void clear_dma_ff(unsigned int dmanr) { if (dmanr<=3) dma_outb(0, DMA1_CLEAR_FF_REG); else dma_outb(0, DMA2_CLEAR_FF_REG); } /* set mode (above) for a specific DMA channel */ static __inline__ void set_dma_mode(unsigned int dmanr, char mode) { if (dmanr<=3) dma_outb(mode | dmanr, DMA1_MODE_REG); else dma_outb(mode | (dmanr&3), DMA2_MODE_REG); } /* set extended mode for a specific DMA channel */ static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode) { if (dmanr<=3) dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG); else dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG); } /* Set only the page register bits of the transfer address. * This is used for successive transfers when we know the contents of * the lower 16 bits of the DMA current address register. */ static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr) { switch(dmanr) { case 0: dma_outb(pagenr, DMA_PAGE_0); dma_outb((pagenr >> 8), DMA_HIPAGE_0); break; case 1: dma_outb(pagenr, DMA_PAGE_1); dma_outb((pagenr >> 8), DMA_HIPAGE_1); break; case 2: dma_outb(pagenr, DMA_PAGE_2); dma_outb((pagenr >> 8), DMA_HIPAGE_2); break; case 3: dma_outb(pagenr, DMA_PAGE_3); dma_outb((pagenr >> 8), DMA_HIPAGE_3); break; case 5: dma_outb(pagenr & 0xfe, DMA_PAGE_5); dma_outb((pagenr >> 8), DMA_HIPAGE_5); break; case 6: dma_outb(pagenr & 0xfe, DMA_PAGE_6); dma_outb((pagenr >> 8), DMA_HIPAGE_6); break; case 7: dma_outb(pagenr & 0xfe, DMA_PAGE_7); dma_outb((pagenr >> 8), DMA_HIPAGE_7); break; } } /* Set transfer address & page bits for specific DMA channel. * Assumes dma flipflop is clear. */ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) { if (dmanr <= 3) { dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); } else { dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); } set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */ } /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for * a specific DMA channel. * You must ensure the parameters are valid. * NOTE: from a manual: "the number of transfers is one more * than the initial word count"! This is taken into account. * Assumes dma flip-flop is clear. * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. */ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) { count--; if (dmanr <= 3) { dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); } else { dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); } } /* Get DMA residue count. After a DMA transfer, this * should return zero. Reading this while a DMA transfer is * still in progress will return unpredictable results. * If called before the channel has been used, it may return 1. * Otherwise, it returns the number of _bytes_ left to transfer. * * Assumes DMA flip-flop is clear. */ static __inline__ int get_dma_residue(unsigned int dmanr) { unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; /* using short to get 16-bit wrap around */ unsigned short count; count = 1 + dma_inb(io_port); count += dma_inb(io_port) << 8; return (dmanr<=3)? count : (count<<1); } /* These are in kernel/dma.c: */ extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ extern void free_dma(unsigned int dmanr); /* release it again */ #endif /* _ASM_DMA_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/elf.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/elf.h?rev=1.1&content-type=text/x-cvsweb-markup Index: elf.h =================================================================== #ifndef __ASMaxp_ELF_H #define __ASMaxp_ELF_H /* * ELF register definitions.. */ /* * The OSF/1 version of <sys/procfs.h> makes gregset_t 46 entries long. * I have no idea why that is so. For now, we just leave it at 33 * (32 general regs + processor status word). */ #define ELF_NGREG 33 #define ELF_NFPREG 32 typedef unsigned long elf_greg_t; typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef double elf_fpreg_t; typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; /* * This is used to ensure we don't load something for the wrong architecture. */ #define elf_check_arch(x) ((x) == EM_ALPHA) /* * These are used to set parameters in the core dumps. */ #define ELF_CLASS ELFCLASS64 #define ELF_DATA ELFDATA2LSB; #define ELF_ARCH EM_ALPHA #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 8192 /* $0 is set by ld.so to a pointer to a function which might be registered using atexit. This provides a mean for the dynamic linker to call DT_FINI functions for shared libraries that have been loaded before the code runs. So that we can use the same startup file with static executables, we start programs with a value of 0 to indicate that there is no such function. */ #define ELF_PLAT_INIT(_r) _r->r0 = 0 /* Use the same format as the OSF/1 procfs interface. The register layout is sane. However, since dump_thread() creates the funky layout that ECOFF coredumps want, we need to undo that layout here. Eventually, it would be nice if the ECOFF core-dump had to do the translation, then ELF_CORE_COPY_REGS() would become trivial and faster. */ #define ELF_CORE_COPY_REGS(_dest,_regs) \ { \ struct user _dump; \ \ dump_thread(_regs, &_dump); \ _dest[ 0] = _dump.regs[EF_V0]; \ _dest[ 1] = _dump.regs[EF_T0]; \ _dest[ 2] = _dump.regs[EF_T1]; \ _dest[ 3] = _dump.regs[EF_T2]; \ _dest[ 4] = _dump.regs[EF_T3]; \ _dest[ 5] = _dump.regs[EF_T4]; \ _dest[ 6] = _dump.regs[EF_T5]; \ _dest[ 7] = _dump.regs[EF_T6]; \ _dest[ 8] = _dump.regs[EF_T7]; \ _dest[ 9] = _dump.regs[EF_S0]; \ _dest[10] = _dump.regs[EF_S1]; \ _dest[11] = _dump.regs[EF_S2]; \ _dest[12] = _dump.regs[EF_S3]; \ _dest[13] = _dump.regs[EF_S4]; \ _dest[14] = _dump.regs[EF_S5]; \ _dest[15] = _dump.regs[EF_S6]; \ _dest[16] = _dump.regs[EF_A0]; \ _dest[17] = _dump.regs[EF_A1]; \ _dest[18] = _dump.regs[EF_A2]; \ _dest[19] = _dump.regs[EF_A3]; \ _dest[20] = _dump.regs[EF_A4]; \ _dest[21] = _dump.regs[EF_A5]; \ _dest[22] = _dump.regs[EF_T8]; \ _dest[23] = _dump.regs[EF_T9]; \ _dest[24] = _dump.regs[EF_T10]; \ _dest[25] = _dump.regs[EF_T11]; \ _dest[26] = _dump.regs[EF_RA]; \ _dest[27] = _dump.regs[EF_T12]; \ _dest[28] = _dump.regs[EF_AT]; \ _dest[29] = _dump.regs[EF_GP]; \ _dest[30] = _dump.regs[EF_SP]; \ _dest[31] = _dump.regs[EF_PC]; /* store PC here */ \ _dest[32] = _dump.regs[EF_PS]; \ } #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/errno.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/errno.h?rev=1.1&content-type=text/x-cvsweb-markup Index: errno.h =================================================================== #ifndef _ALPHA_ERRNO_H #define _ALPHA_ERRNO_H #define EPERM 1 /* Operation not permitted */ #define ENOENT 2 /* No such file or directory */ #define ESRCH 3 /* No such process */ #define EINTR 4 /* Interrupted system call */ #define EIO 5 /* I/O error */ #define ENXIO 6 /* No such device or address */ #define E2BIG 7 /* Arg list too long */ #define ENOEXEC 8 /* Exec format error */ #define EBADF 9 /* Bad file number */ #define ECHILD 10 /* No child processes */ #define EDEADLK 11 /* Resource deadlock would occur */ #define ENOMEM 12 /* Out of memory */ #define EACCES 13 /* Permission denied */ #define EFAULT 14 /* Bad address */ #define ENOTBLK 15 /* Block device required */ #define EBUSY 16 /* Device or resource busy */ #define EEXIST 17 /* File exists */ #define EXDEV 18 /* Cross-device link */ #define ENODEV 19 /* No such device */ #define ENOTDIR 20 /* Not a directory */ #define EISDIR 21 /* Is a directory */ #define EINVAL 22 /* Invalid argument */ #define ENFILE 23 /* File table overflow */ #define EMFILE 24 /* Too many open files */ #define ENOTTY 25 /* Not a typewriter */ #define ETXTBSY 26 /* Text file busy */ #define EFBIG 27 /* File too large */ #define ENOSPC 28 /* No space left on device */ #define ESPIPE 29 /* Illegal seek */ #define EROFS 30 /* Read-only file system */ #define EMLINK 31 /* Too many links */ #define EPIPE 32 /* Broken pipe */ #define EDOM 33 /* Math argument out of domain of func */ #define ERANGE 34 /* Math result not representable */ #define EAGAIN 35 /* Try again */ #define EWOULDBLOCK EAGAIN /* Operation would block */ #define EINPROGRESS 36 /* Operation now in progress */ #define EALREADY 37 /* Operation already in progress */ #define ENOTSOCK 38 /* Socket operation on non-socket */ #define EDESTADDRREQ 39 /* Destination address required */ #define EMSGSIZE 40 /* Message too long */ #define EPROTOTYPE 41 /* Protocol wrong type for socket */ #define ENOPROTOOPT 42 /* Protocol not available */ #define EPROTONOSUPPORT 43 /* Protocol not supported */ #define ESOCKTNOSUPPORT 44 /* Socket type not supported */ #define EOPNOTSUPP 45 /* Operation not supported on transport endpoint */ #define EPFNOSUPPORT 46 /* Protocol family not supported */ #define EAFNOSUPPORT 47 /* Address family not supported by protocol */ #define EADDRINUSE 48 /* Address already in use */ #define EADDRNOTAVAIL 49 /* Cannot assign requested address */ #define ENETDOWN 50 /* Network is down */ #define ENETUNREACH 51 /* Network is unreachable */ #define ENETRESET 52 /* Network dropped connection because of reset */ #define ECONNABORTED 53 /* Software caused connection abort */ #define ECONNRESET 54 /* Connection reset by peer */ #define ENOBUFS 55 /* No buffer space available */ #define EISCONN 56 /* Transport endpoint is already connected */ #define ENOTCONN 57 /* Transport endpoint is not connected */ #define ESHUTDOWN 58 /* Cannot send after transport endpoint shutdown */ #define ETOOMANYREFS 59 /* Too many references: cannot splice */ #define ETIMEDOUT 60 /* Connection timed out */ #define ECONNREFUSED 61 /* Connection refused */ #define ELOOP 62 /* Too many symbolic links encountered */ #define ENAMETOOLONG 63 /* File name too long */ #define EHOSTDOWN 64 /* Host is down */ #define EHOSTUNREACH 65 /* No route to host */ #define ENOTEMPTY 66 /* Directory not empty */ #define EUSERS 68 /* Too many users */ #define EDQUOT 69 /* Quota exceeded */ #define ESTALE 70 /* Stale NFS file handle */ #define EREMOTE 71 /* Object is remote */ #define ENOLCK 77 /* No record locks available */ #define ENOSYS 78 /* Function not implemented */ #define ENOMSG 80 /* No message of desired type */ #define EIDRM 81 /* Identifier removed */ #define ENOSR 82 /* Out of streams resources */ #define ETIME 83 /* Timer expired */ #define EBADMSG 84 /* Not a data message */ #define EPROTO 85 /* Protocol error */ #define ENODATA 86 /* No data available */ #define ENOSTR 87 /* Device not a stream */ #define ENOPKG 92 /* Package not installed */ #define EILSEQ 116 /* Illegal byte sequence */ /* The following are just random noise.. */ #define ECHRNG 88 /* Channel number out of range */ #define EL2NSYNC 89 /* Level 2 not synchronized */ #define EL3HLT 90 /* Level 3 halted */ #define EL3RST 91 /* Level 3 reset */ #define ELNRNG 93 /* Link number out of range */ #define EUNATCH 94 /* Protocol driver not attached */ #define ENOCSI 95 /* No CSI structure available */ #define EL2HLT 96 /* Level 2 halted */ #define EBADE 97 /* Invalid exchange */ #define EBADR 98 /* Invalid request descriptor */ #define EXFULL 99 /* Exchange full */ #define ENOANO 100 /* No anode */ #define EBADRQC 101 /* Invalid request code */ #define EBADSLT 102 /* Invalid slot */ #define EDEADLOCK EDEADLK #define EBFONT 104 /* Bad font file format */ #define ENONET 105 /* Machine is not on the network */ #define ENOLINK 106 /* Link has been severed */ #define EADV 107 /* Advertise error */ #define ESRMNT 108 /* Srmount error */ #define ECOMM 109 /* Communication error on send */ #define EMULTIHOP 110 /* Multihop attempted */ #define EDOTDOT 111 /* RFS specific error */ #define EOVERFLOW 112 /* Value too large for defined data type */ #define ENOTUNIQ 113 /* Name not unique on network */ #define EBADFD 114 /* File descriptor in bad state */ #define EREMCHG 115 /* Remote address changed */ #define EUCLEAN 117 /* Structure needs cleaning */ #define ENOTNAM 118 /* Not a XENIX named type file */ #define ENAVAIL 119 /* No XENIX semaphores available */ #define EISNAM 120 /* Is a named type file */ #define EREMOTEIO 121 /* Remote I/O error */ #define ELIBACC 122 /* Can not access a needed shared library */ #define ELIBBAD 123 /* Accessing a corrupted shared library */ #define ELIBSCN 124 /* .lib section in a.out corrupted */ #define ELIBMAX 125 /* Attempting to link in too many shared libraries */ #define ELIBEXEC 126 /* Cannot exec a shared library directly */ #define ERESTART 127 /* Interrupted system call should be restarted */ #define ESTRPIPE 128 /* Streams pipe error */ #define ENOMEDIUM 129 /* No medium found */ #define EMEDIUMTYPE 130 /* Wrong medium type */ #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/fcntl.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/fcntl.h?rev=1.1&content-type=text/x-cvsweb-markup Index: fcntl.h =================================================================== #ifndef _ALPHA_FCNTL_H #define _ALPHA_FCNTL_H /* open/fcntl - O_SYNC is only implemented on blocks devices and on files located on an ext2 file system */ #define O_ACCMODE 0003 #define O_RDONLY 00 #define O_WRONLY 01 #define O_RDWR 02 #define O_CREAT 01000 /* not fcntl */ #define O_TRUNC 02000 /* not fcntl */ #define O_EXCL 04000 /* not fcntl */ #define O_NOCTTY 010000 /* not fcntl */ #define O_NONBLOCK 00004 #define O_APPEND 00010 #define O_NDELAY O_NONBLOCK #define O_SYNC 040000 #define FASYNC 020000 /* fcntl, for BSD compatibility */ #define F_DUPFD 0 /* dup */ #define F_GETFD 1 /* get f_flags */ #define F_SETFD 2 /* set f_flags */ #define F_GETFL 3 /* more flags (cloexec) */ #define F_SETFL 4 #define F_GETLK 7 #define F_SETLK 8 #define F_SETLKW 9 #define F_SETOWN 5 /* for sockets. */ #define F_GETOWN 6 /* for sockets. */ /* for F_[GET|SET]FL */ #define FD_CLOEXEC 1 /* actually anything with low bit set goes */ /* for posix fcntl() and lockf() */ #define F_RDLCK 1 #define F_WRLCK 2 #define F_UNLCK 8 /* for old implementation of bsd flock () */ #define F_EXLCK 16 /* or 3 */ #define F_SHLCK 32 /* or 4 */ /* operations for bsd flock(), also used by the kernel implementation */ #define LOCK_SH 1 /* shared lock */ #define LOCK_EX 2 /* exclusive lock */ #define LOCK_NB 4 /* or'd with one of the above to prevent blocking */ #define LOCK_UN 8 /* remove lock */ struct flock { short l_type; short l_whence; __kernel_off_t l_start; __kernel_off_t l_len; __kernel_pid_t l_pid; }; #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/floppy.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/floppy.h?rev=1.1&content-type=text/x-cvsweb-markup Index: floppy.h =================================================================== /* * Architecture specific parts of the Floppy driver * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995 */ #ifndef __ASM_ALPHA_FLOPPY_H #define __ASM_ALPHA_FLOPPY_H #include <linux/config.h> #define fd_inb(port) inb_p(port) #define fd_outb(port,value) outb_p(port,value) #define fd_enable_dma() enable_dma(FLOPPY_DMA) #define fd_disable_dma() disable_dma(FLOPPY_DMA) #define fd_request_dma() request_dma(FLOPPY_DMA,"floppy") #define fd_free_dma() free_dma(FLOPPY_DMA) #define fd_clear_dma_ff() clear_dma_ff(FLOPPY_DMA) #define fd_set_dma_mode(mode) set_dma_mode(FLOPPY_DMA,mode) #define fd_set_dma_addr(addr) set_dma_addr(FLOPPY_DMA,addr) #define fd_set_dma_count(count) set_dma_count(FLOPPY_DMA,count) #define fd_enable_irq() enable_irq(FLOPPY_IRQ) #define fd_disable_irq() disable_irq(FLOPPY_IRQ) #define fd_cacheflush(addr,size) /* nothing */ #define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt, \ SA_INTERRUPT|SA_SAMPLE_RANDOM, \ "floppy", NULL) #define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); __inline__ void virtual_dma_init(void) { /* Nothing to do on an Alpha */ } static int FDC1 = 0x3f0; static int FDC2 = -1; /* * Again, the CMOS information doesn't work on the alpha.. */ #define FLOPPY0_TYPE 6 #define FLOPPY1_TYPE 0 #define N_FDC 2 #define N_DRIVE 8 /* * Most Alphas have no problems with floppy DMA crossing 64k borders. Sigh... */ #if defined(CONFIG_ALPHA_XL) || defined(CONFIG_ALPHA_RUFFIAN) #define CROSS_64KB(a,s) \ ((unsigned long)(a)/0x10000 != ((unsigned long)(a) + (s) - 1) / 0x10000) #else /* XL || RUFFIAN */ #define CROSS_64KB(a,s) (0) #endif /* XL || RUFFIAN */ #endif /* __ASM_ALPHA_FLOPPY_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/fpu.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/fpu.h?rev=1.1&content-type=text/x-cvsweb-markup Index: fpu.h =================================================================== #ifndef __ASM_ALPHA_FPU_H #define __ASM_ALPHA_FPU_H /* * Alpha floating-point control register defines: */ #define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */ #define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */ #define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */ #define FPCR_INV (1UL<<52) /* invalid operation */ #define FPCR_DZE (1UL<<53) /* division by zero */ #define FPCR_OVF (1UL<<54) /* overflow */ #define FPCR_UNF (1UL<<55) /* underflow */ #define FPCR_INE (1UL<<56) /* inexact */ #define FPCR_IOV (1UL<<57) /* integer overflow */ #define FPCR_UNDZ (1UL<<60) /* underflow to zero (opt.) */ #define FPCR_UNFD (1UL<<61) /* underflow disable (opt.) */ #define FPCR_INED (1UL<<62) /* inexact disable (opt.) */ #define FPCR_SUM (1UL<<63) /* summary bit */ #define FPCR_DYN_SHIFT 58 /* first dynamic rounding mode bit */ #define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT) /* towards 0 */ #define FPCR_DYN_MINUS (0x1UL << FPCR_DYN_SHIFT) /* towards -INF */ #define FPCR_DYN_NORMAL (0x2UL << FPCR_DYN_SHIFT) /* towards nearest */ #define FPCR_DYN_PLUS (0x3UL << FPCR_DYN_SHIFT) /* towards +INF */ #define FPCR_DYN_MASK (0x3UL << FPCR_DYN_SHIFT) #define FPCR_MASK 0xfffe000000000000 /* * IEEE trap enables are implemented in software. These per-thread * bits are stored in the "flags" field of "struct thread_struct". * Thus, the bits are defined so as not to conflict with the * floating-point enable bit (which is architected). On top of that, * we want to make these bits compatible with OSF/1 so * ieee_set_fp_control() etc. can be implemented easily and * compatibly. The corresponding definitions are in * /usr/include/machine/fpu.h under OSF/1. */ #define IEEE_TRAP_ENABLE_INV (1<<1) /* invalid op */ #define IEEE_TRAP_ENABLE_DZE (1<<2) /* division by zero */ #define IEEE_TRAP_ENABLE_OVF (1<<3) /* overflow */ #define IEEE_TRAP_ENABLE_UNF (1<<4) /* underflow */ #define IEEE_TRAP_ENABLE_INE (1<<5) /* inexact */ #define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\ IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\ IEEE_TRAP_ENABLE_INE) /* status bits coming from fpcr: */ #define IEEE_STATUS_INV (1<<17) #define IEEE_STATUS_DZE (1<<18) #define IEEE_STATUS_OVF (1<<19) #define IEEE_STATUS_UNF (1<<20) #define IEEE_STATUS_INE (1<<21) #define IEEE_STATUS_MASK (IEEE_STATUS_INV | IEEE_STATUS_DZE | \ IEEE_STATUS_OVF | IEEE_STATUS_UNF | \ IEEE_STATUS_INE) #define IEEE_SW_MASK (IEEE_TRAP_ENABLE_MASK | IEEE_STATUS_MASK) #define IEEE_STATUS_TO_EXCSUM_SHIFT 16 #define IEEE_INHERIT (1UL<<63) /* inherit on thread create? */ /* * Convert the software IEEE trap enables and status bits into the * hardware fpcr format. */ static inline unsigned long ieee_sw_to_fpcr(unsigned long sw) { unsigned long fpcw; fpcw = (sw & IEEE_STATUS_MASK) << 35; fpcw |= sw & IEEE_STATUS_MASK ? FPCR_SUM : 0; fpcw |= (~sw & (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE | IEEE_TRAP_ENABLE_OVF)) << 48; fpcw |= (~sw & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE)) << 57; return fpcw; } #endif /* __ASM_ALPHA_FPU_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/gentrap.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/gentrap.h?rev=1.1&content-type=text/x-cvsweb-markup Index: gentrap.h =================================================================== #ifndef _ASMAXP_GENTRAP_H #define _ASMAXP_GENTRAP_H /* * Definitions for gentrap causes. They are generated by user-level * programs and therefore should be compatible with the corresponding * OSF/1 definitions. */ #define GEN_INTOVF -1 /* integer overflow */ #define GEN_INTDIV -2 /* integer division by zero */ #define GEN_FLTOVF -3 /* fp overflow */ #define GEN_FLTDIV -4 /* fp division by zero */ #define GEN_FLTUND -5 /* fp underflow */ #define GEN_FLTINV -6 /* invalid fp operand */ #define GEN_FLTINE -7 /* inexact fp operand */ #define GEN_DECOVF -8 /* decimal overflow (for COBOL??) */ #define GEN_DECDIV -9 /* decimal division by zero */ #define GEN_DECINV -10 /* invalid decimal operand */ #define GEN_ROPRAND -11 /* reserved operand */ #define GEN_ASSERTERR -12 /* assertion error */ #define GEN_NULPTRERR -13 /* null pointer error */ #define GEN_STKOVF -14 /* stack overflow */ #define GEN_STRLENERR -15 /* string length error */ #define GEN_SUBSTRERR -16 /* substring error */ #define GEN_RANGERR -17 /* range error */ #define GEN_SUBRNG -18 #define GEN_SUBRNG1 -19 #define GEN_SUBRNG2 -20 #define GEN_SUBRNG3 -21 /* these report range errors for */ #define GEN_SUBRNG4 -22 /* subscripting (indexing) at levels 0..7 */ #define GEN_SUBRNG5 -23 #define GEN_SUBRNG6 -24 #define GEN_SUBRNG7 -25 /* the remaining codes (-26..-1023) are reserved. */ #endif /* _ASMAXP_GENTRAP_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/hwrpb.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/hwrpb.h?rev=1.1&content-type=text/x-cvsweb-markup Index: hwrpb.h =================================================================== #ifndef _HWRPB_H #define _HWRPB_H #define INIT_HWRPB ((struct hwrpb_struct *) 0x10000000) /* * DEC processor types for Alpha systems. Found in HWRPB. * These values are architected. */ #define EV3_CPU 1 /* EV3 */ #define EV4_CPU 2 /* EV4 (21064) */ #define LCA4_CPU 4 /* LCA4 (21066/21068) */ #define EV5_CPU 5 /* EV5 (21164) */ #define EV45_CPU 6 /* EV4.5 (21064/xxx) */ #define EV56_CPU 7 /* EV5.6 (21164) */ #define EV6_CPU 8 /* EV6 (21164) */ #define PCA56_CPU 9 /* PCA56 (21164PC) */ #define PCA57_CPU 10 /* PCA57 (21164??) */ /* * DEC system types for Alpha systems. Found in HWRPB. * These values are architected. */ #define ST_ADU 1 /* Alpha ADU systype */ #define ST_DEC_4000 2 /* Cobra systype */ #define ST_DEC_7000 3 /* Ruby systype */ #define ST_DEC_3000_500 4 /* Flamingo systype */ #define ST_DEC_2000_300 6 /* Jensen systype */ #define ST_DEC_3000_300 7 /* Pelican systype */ #define ST_DEC_2100_A500 9 /* Sable systype */ #define ST_DEC_AXPVME_64 10 /* AXPvme system type */ #define ST_DEC_AXPPCI_33 11 /* NoName system type */ #define ST_DEC_TLASER 12 /* Turbolaser systype */ #define ST_DEC_2100_A50 13 /* Avanti systype */ #define ST_DEC_ALCOR 15 /* Alcor (EV5) systype */ #define ST_DEC_1000 17 /* Mikasa systype */ #define ST_DEC_EB64 18 /* EB64 systype */ #define ST_DEC_EB66 19 /* EB66 systype */ #define ST_DEC_EB64P 20 /* EB64+ systype */ #define ST_DEC_BURNS 21 /* laptop systype */ #define ST_DEC_RAWHIDE 22 /* Rawhide systype */ #define ST_DEC_K2 23 /* K2 systype */ #define ST_DEC_LYNX 24 /* Lynx systype */ #define ST_DEC_XL 25 /* Alpha XL systype */ #define ST_DEC_EB164 26 /* EB164 systype */ #define ST_DEC_NORITAKE 27 /* Noritake systype */ #define ST_DEC_CORTEX 28 /* Cortex systype */ #define ST_DEC_MIATA 30 /* Miata systype */ #define ST_DEC_XXM 31 /* XXM systype */ #define ST_DEC_TAKARA 32 /* Takara systype */ #define ST_DEC_YUKON 33 /* Yukon systype */ #define ST_DEC_TSUNAMI 34 /* Tsunami systype */ #define ST_DEC_WILDFIRE 35 /* Wildfire systype */ #define ST_DEC_CUSCO 36 /* CUSCO systype */ /* UNOFFICIAL!!! */ #define ST_UNOFFICIAL_BIAS 100 #define ST_DTI_RUFFIAN 101 /* RUFFIAN systype */ struct pcb_struct { unsigned long ksp; unsigned long usp; unsigned long ptbr; unsigned int pcc; unsigned int asn; unsigned long unique; unsigned long flags; unsigned long res1, res2; }; struct percpu_struct { unsigned long hwpcb[16]; unsigned long flags; unsigned long pal_mem_size; unsigned long pal_scratch_size; unsigned long pal_mem_pa; unsigned long pal_scratch_pa; unsigned long pal_revision; unsigned long type; unsigned long variation; unsigned long revision; unsigned long serial_no[2]; unsigned long logout_area_pa; unsigned long logout_area_len; unsigned long halt_PCBB; unsigned long halt_PC; unsigned long halt_PS; unsigned long halt_arg; unsigned long halt_ra; unsigned long halt_pv; unsigned long halt_reason; unsigned long res; unsigned long ipc_buffer[21]; unsigned long palcode_avail[16]; unsigned long compatibility; }; struct procdesc_struct { unsigned long weird_vms_stuff; unsigned long address; }; struct vf_map_struct { unsigned long va; unsigned long pa; unsigned long count; }; struct crb_struct { struct procdesc_struct * dispatch_va; struct procdesc_struct * dispatch_pa; struct procdesc_struct * fixup_va; struct procdesc_struct * fixup_pa; /* virtual->physical map */ unsigned long map_entries; unsigned long map_pages; struct vf_map_struct map[1]; }; struct memclust_struct { unsigned long start_pfn; unsigned long numpages; unsigned long numtested; unsigned long bitmap_va; unsigned long bitmap_pa; unsigned long bitmap_chksum; unsigned long usage; }; struct memdesc_struct { unsigned long chksum; unsigned long optional_pa; unsigned long numclusters; struct memclust_struct cluster[0]; }; struct dsr_struct { long smm; /* SMM nubber used by LMF */ unsigned long lurt_off; /* offset to LURT table */ unsigned long sysname_off; /* offset to sysname char count */ }; struct hwrpb_struct { unsigned long phys_addr; /* check: physical address of the hwrpb */ unsigned long id; /* check: "HWRPB\0\0\0" */ unsigned long revision; unsigned long size; /* size of hwrpb */ unsigned long cpuid; unsigned long pagesize; /* 8192, I hope */ unsigned long pa_bits; /* number of physical address bits */ unsigned long max_asn; unsigned char ssn[16]; /* system serial number: big bother is watching */ unsigned long sys_type; unsigned long sys_variation; unsigned long sys_revision; unsigned long intr_freq; /* interval clock frequency * 4096 */ unsigned long cycle_freq; /* cycle counter frequency */ unsigned long vptb; /* Virtual Page Table Base address */ unsigned long res1; unsigned long tbhb_offset; /* Translation Buffer Hint Block */ unsigned long nr_processors; unsigned long processor_size; unsigned long processor_offset; unsigned long ctb_nr; unsigned long ctb_size; /* console terminal block size */ unsigned long ctbt_offset; /* console terminal block table offset */ unsigned long crb_offset; /* console callback routine block */ unsigned long mddt_offset; /* memory data descriptor table */ unsigned long cdb_offset; /* configuration data block (or NULL) */ unsigned long frut_offset; /* FRU table (or NULL) */ void (*save_terminal)(unsigned long); unsigned long save_terminal_data; void (*restore_terminal)(unsigned long); unsigned long restore_terminal_data; void (*CPU_restart)(unsigned long); unsigned long CPU_restart_data; unsigned long res2; unsigned long res3; unsigned long chksum; unsigned long rxrdy; unsigned long txrdy; unsigned long dsr_offset; /* "Dynamic System Recognition Data Block Table" */ }; #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-alpha/io.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-alpha/io.h?rev=1.1&content-type=text/x-cvsweb-markup Index: io.h =================================================================== #ifndef __ALPHA_IO_H #define __ALPHA_IO_H #include <linux/config.h> #include <asm/system.h> /* We don't use IO slowdowns on the alpha, but.. */ #define __SLOW_DOWN_IO do { } while (0) #define SLOW_DOWN_IO do { } while (0) /* * The hae (hardware address extension) register is used to * access high IO addresses. To avoid doing an external cycle * every time we need to set the hae, we have a hae cache in * memory. The kernel entry code makes sure that the hae is * preserved across interrupts, so it is safe to set the hae * once and then depend on it staying the same in kernel code. */ extern struct hae { unsigned long cache; unsigned long *reg; } hae; /* * Virtual -> physical identity mapping starts at this offset */ #ifdef USE_48_BIT_KSEG #define IDENT_ADDR (0xffff800000000000UL) #else #define IDENT_ADDR (0xfffffc0000000000UL) #endif #ifdef __KERNEL__ /* * We try to avoid hae updates (thus the cache), but when we * do need to update the hae, we need to do it atomically, so * that any interrupts wouldn't get confused with the hae * register not being up-to-date with respect to the hardware * value. */ extern inline void set_hae(unsigned long new_hae) { unsigned long ipl = swpipl(7); hae.cache = new_hae; *hae.reg = new_hae; mb(); new_hae = *hae.reg; /* read to make sure it was written */ setipl(ipl); } /* * Change virtual addresses to physical addresses and vv. */ extern inline unsigned long virt_to_phys(volatile void * address) { return 0xffffffffUL & (unsigned