|
Message
From: cvs at opencores.org<cvs@o...>
Date: Wed Nov 30 18:31:12 CET 2005
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/05/11 30:18:31 Added: jop/vhdl/scio sc_test_slave.vhd sc_test_top.vhd
Log:
SimpCon IO test
Revision Changes Path
1.1 jop/vhdl/scio/sc_test_slave.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/scio/sc_test_slave.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: sc_test_slave.vhd
===================================================================
--
-- sc_test_slave.vhd
--
-- A simple test slave for the SimpCon interface
--
-- Author: Martin Schoeberl martin@j...
--
--
-- resources on Cyclone
--
-- xx LCs, max xx MHz
--
--
-- 2005-11-29 first version
--
-- todo:
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sc_test_slave is
generic (addr_bits : integer);
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon interface
address : in std_logic_vector(addr_bits-1 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd, wr : in std_logic;
rd_data : out std_logic_vector(31 downto 0);
rdy_cnt : out unsigned(1 downto 0)
);
end sc_test_slave;
architecture rtl of sc_test_slave is
signal xyz : std_logic_vector(31 downto 0);
signal cnt : unsigned(31 downto 0);
begin
rdy_cnt <= "00"; -- no wait states
--
-- The registered MUX is all we need for a SimpCon read.
-- The read data is stored in registered rd_data.
--
process(clk, reset)
begin
if (reset='1') then
rd_data <= (others => '0');
elsif rising_edge(clk) then
if rd='1' then
-- that's our very simple address decoder
if address(0)='0' then
rd_data <= std_logic_vector(cnt);
else
rd_data <= xyz;
end if;
end if;
end if;
end process;
--
-- SimpCon write is very simple
--
process(clk, reset)
begin
if (reset='1') then
xyz <= (others => '0');
cnt <= (others => '0');
elsif rising_edge(clk) then
if wr='1' then
xyz <= wr_data;
end if;
cnt <= cnt+1;
end if;
end process;
end rtl;
1.1 jop/vhdl/scio/sc_test_top.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/scio/sc_test_top.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: sc_test_top.vhd
===================================================================
--
-- scio_test_top.vhd
--
-- The top level to test SimpCon IO devices.
-- Do the address decoding here for the various slaves.
--
-- Author: Martin Schoeberl martin@j...
--
--
-- 2005-11-30 first version with two simple test slaves
--
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.jop_types.all;
entity scio is
generic (addr_bits : integer);
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon interface
address : in std_logic_vector(addr_bits-1 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd, wr : in std_logic;
rd_data : out std_logic_vector(31 downto 0);
rdy_cnt : out unsigned(1 downto 0)
);
end scio;
architecture rtl of scio is
constant SLAVE_CNT : integer := 4;
-- SLAVE_CNT <= 2**DECODE_BITS
constant DECODE_BITS : integer := 2;
-- number of bits that can be used inside the slave
constant SLAVE_ADDR_BITS : integer := 4;
type slave_bit is array(0 to SLAVE_CNT-1) of std_logic;
signal sc_rd, sc_wr : slave_bit;
type slave_dout is array(0 to SLAVE_CNT-1) of std_logic_vector(31 downto 0);
signal sc_dout : slave_dout;
type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0);
signal sc_rdy_cnt : slave_rdy_cnt;
signal sel, sel_reg : integer range 0 to 2**DECODE_BITS-1;
begin
assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio";
sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));
-- What happens when sel_reg > SLAVE_CNT-1??
rd_data <= sc_dout(sel_reg);
rdy_cnt <= sc_rdy_cnt(sel_reg);
--
-- Connect SLAVE_CNT simple test slaves
--
gsl: for i in 0 to SLAVE_CNT-1 generate
sc_rd(i) <= rd when i=sel else '0';
sc_wr(i) <= wr when i=sel else '0';
scsl: entity work.sc_test_slave
generic map (
-- shall we use less address bits inside the slaves?
addr_bits => SLAVE_ADDR_BITS
)
port map (
clk => clk,
reset => reset,
address => address(SLAVE_ADDR_BITS-1 downto 0),
wr_data => wr_data,
rd => sc_rd(i),
wr => sc_wr(i),
rd_data => sc_dout(i),
rdy_cnt => sc_rdy_cnt(i)
);
end generate;
--
-- Register read mux selector
--
process(clk, reset)
begin
if (reset='1') then
sel_reg <= 0;
elsif rising_edge(clk) then
if rd='1' then
sel_reg <= sel;
end if;
end if;
end process;
end rtl;
|
 |
Browse
