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Message
From: cvs at opencores.org<cvs@o...>
Date: Wed Nov 30 13:36:28 CET 2005
Subject: [cvs-checkins] MODIFIED: simpcon ...
Date: 00/05/11 30:13:36 Modified: simpcon/vhdl sc_test_top.vhd
Log:
Generic decoding and data mux
Revision Changes Path
1.2 simpcon/vhdl/sc_test_top.vhd
http://www.opencores.org/cvsweb.shtml/simpcon/vhdl/sc_test_top.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: sc_test_top.vhd
===================================================================
RCS file: /cvsroot/martin/simpcon/vhdl/sc_test_top.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- sc_test_top.vhd 30 Nov 2005 10:46:49 -0000 1.1
+++ sc_test_top.vhd 30 Nov 2005 12:36:27 -0000 1.2
@@ -39,7 +39,10 @@
architecture rtl of scio is
- constant SLAVE_CNT : integer := 2;
+ constant SLAVE_CNT : integer := 4;
+ -- SLAVE_CNT <= 2**DECODE_BITS
+ constant DECODE_BITS : integer := 2;
+ -- number of bits that can be used inside the slave
constant SLAVE_ADDR_BITS : integer := 4;
type slave_bit is array(0 to SLAVE_CNT-1) of std_logic;
@@ -51,15 +54,27 @@
type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0);
signal sc_rdy_cnt : slave_rdy_cnt;
- signal rd_mux : std_logic;
+ signal sel, sel_reg : integer range 0 to 2**DECODE_BITS-1;
begin
+ assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio";
+
+ sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));
+
+ -- What happens when sel_reg > SLAVE_CNT-1??
+ rd_data <= sc_dout(sel_reg);
+ rdy_cnt <= sc_rdy_cnt(sel_reg);
+
--
- -- Connect two simple test slaves
+ -- Connect SLAVE_CNT simple test slaves
--
gsl: for i in 0 to SLAVE_CNT-1 generate
- wbsl: entity work.sc_test_slave
+
+ sc_rd(i) <= rd when i=sel else '0';
+ sc_wr(i) <= wr when i=sel else '0';
+
+ scsl: entity work.sc_test_slave
generic map (
-- shall we use less address bits inside the slaves?
addr_bits => SLAVE_ADDR_BITS
@@ -77,60 +92,19 @@
);
end generate;
-
-
---
--- Address decoding
---
-process(address, rd, wr)
-begin
-
- -- How can we formulate this more elegant?
- sc_rd(0) <= '0';
- sc_wr(0) <= '0';
- sc_rd(1) <= '0';
- sc_wr(1) <= '0';
-
- if address(SLAVE_ADDR_BITS)='0' then
- sc_rd(0) <= rd;
- sc_wr(0) <= wr;
- else
- sc_rd(1) <= rd;
- sc_wr(1) <= wr;
- end if;
-
-end process;
-
---
--- Read mux selector
---
-process(clk, reset)
-begin
-
+ --
+ -- Register read mux selector
+ --
+ process(clk, reset)
+ begin
if (reset='1') then
- rd_mux <= '0';
+ sel_reg <= 0;
elsif rising_edge(clk) then
if rd='1' then
- rd_mux <= address(SLAVE_ADDR_BITS);
+ sel_reg <= sel;
end if;
end if;
-end process;
-
---
--- Read data and rdy_cnt mux
---
--- Or should we simple or the rdy_cnt values?
---
-process(rd_mux, sc_dout, sc_rdy_cnt)
-begin
+ end process;
- if rd_mux='0' then
- rd_data <= sc_dout(0);
- rdy_cnt <= sc_rdy_cnt(0);
- else
- rd_data <= sc_dout(1);
- rdy_cnt <= sc_rdy_cnt(1);
- end if;
-end process;
end rtl;
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