Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Thu Nov 24 21:52:56 CET 2005
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/05/11 24:21:52

Added: jop/vhdl/xilinx xram.vhd xs3_jbc.vhd
Log:
Use mem_sc and sc_sram32 with block cache for S3. No more Spartan

specific main memory module.


Revision Changes Path
1.1 jop/vhdl/xilinx/xram.vhd

http://www.opencores.org/cvsweb.shtml/jop/vhdl/xilinx/xram.vhd?rev=1.1&content-type=text/x-cvsweb-markup

Index: xram.vhd
===================================================================
--
-- xram_xc2s_xcv.vhd
--
-- internal memory for JOP3
-- Version for Xilinx Spartan II/IIe and Virtex Families
--
-- Changes:
-- 2003-12-29 EA - modified for Xilinx ISE to use Block SelectRAM+
--
--

Library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;
library unisim;
use unisim.vcomponents.all;

entity ram is
generic (width : integer := 32; addr_width : integer := 8);
port (
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(addr_width-1 downto 0);
rdaddress : in std_logic_vector(addr_width-1 downto 0);
wren : in std_logic;
clock : in std_logic;

q : out std_logic_vector(width-1 downto 0)
);
end ram ;

--
-- registered and delayed wraddress, wren
-- registered din
-- registered rdaddress
-- unregistered dout
--
-- with normal clock on wrclock:
-- => read during write on same address!!! (ok in ACEX)
-- for Cyclone use not clock for wrclock, but works also on ACEX
--
architecture rtl of ram is

signal wraddr_dly : std_logic_vector(addr_width-1 downto 0);
signal wren_dly : std_logic;

COMPONENT xram_block
PORT(
a_rst : IN std_logic;
a_clk : IN std_logic;
a_en : IN std_logic;
a_wr : IN std_logic;
a_addr : IN std_logic_vector(7 downto 0);
a_din : IN std_logic_vector(31 downto 0);
b_rst : IN std_logic;
b_clk : IN std_logic;
b_en : IN std_logic;
b_wr : IN std_logic;
b_addr : IN std_logic_vector(7 downto 0);
b_din : IN std_logic_vector(31 downto 0);
a_dout : OUT std_logic_vector(31 downto 0);
b_dout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;


begin

--
-- delay wr addr and ena because of registerd indata
--
process(clock) begin

if rising_edge(clock) then
wraddr_dly <= wraddress;
wren_dly <= wren;
end if;
end process;

cmp_xram_block: xram_block PORT MAP(
a_rst => '0',
a_clk => not clock,
a_en => '1',
a_wr => wren_dly,
a_addr => wraddr_dly,
a_din => data,
a_dout => open, b_rst => '0', b_clk => clock, b_en => '1', b_wr => '0', b_addr => rdaddress, b_din => X"00000000", b_dout => q ); end rtl; 1.1 jop/vhdl/xilinx/xs3_jbc.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/xilinx/xs3_jbc.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: xs3_jbc.vhd =================================================================== -- -- xs3_jbc.vhd -- -- bytecode memory/cache for JOP -- Version for Xilinx Spartan-3 -- -- address, data in are registered -- data out is unregistered -- -- -- Changes: -- 2003-08-14 load start address with jpc_wr and do autoincrement -- load 32 bit data and do the 4 byte writes serial -- 2005-02-17 extracted again from mem32.vhd -- 2005-05-03 address width is jpc_width -- 2005-11-24 adapted for S3 -- -- library ieee; use ieee.std_logic_1164.all; entity jbc is generic (jpc_width : integer); port ( clk : in std_logic; data : in std_logic_vector(31 downto 0); rd_addr : in std_logic_vector(jpc_width-1 downto 0); wr_addr : in std_logic_vector(jpc_width-3 downto 0); wr_en : in std_logic; q : out std_logic_vector(7 downto 0) ); end jbc; -- -- registered wraddress, wren -- registered din -- registered rdaddress -- unregistered dout -- architecture rtl of jbc is ----- Component RAMB16_S9_S36 ----- component RAMB16_S9_S36 -- generic ( WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; INIT_A : bit_vector := X"000"; SRVAL_A : bit_vector := X"000"; INIT_B : bit_vector := X"000000000"; SRVAL_B : bit_vector := X"000000000" ); -- port (DIA : in STD_LOGIC_VECTOR (7 downto 0); DIB : in STD_LOGIC_VECTOR (31 downto 0); DIPA : in STD_LOGIC_VECTOR (0 downto 0); DIPB : in STD_LOGIC_VECTOR (3 downto 0); ENA : in STD_logic; ENB : in STD_logic; WEA : in STD_logic; WEB : in STD_logic; SSRA : in STD_logic; SSRB : in STD_logic; CLKA : in STD_logic; CLKB : in STD_logic; ADDRA : in STD_LOGIC_VECTOR (10 downto 0); ADDRB : in STD_LOGIC_VECTOR (8 downto 0); DOA : out STD_LOGIC_VECTOR (7 downto 0); DOB : out STD_LOGIC_VECTOR (31 downto 0); DOPA : out STD_LOGIC_VECTOR (0 downto 0); DOPB : out STD_LOGIC_VECTOR (3 downto 0) ); end component; begin -- the block ram is 2KB assert jpc_width=11 report "Xilinx jbc is fixed to 2KB - use jbc_width of 11"; cmp_jbc : RAMB16_S9_S36 port map ( DIA => "00000000", DIB => data, DIPA => "0", DIPB => "0000", ENA => '1', ENB => '1', WEA => '0', WEB => wr_en, SSRA => '0', SSRB => '0', CLKA => clk, CLKB => clk, ADDRA => rd_addr, ADDRB => wr_addr, DOA => q, DOB => open, DOPA => open, DOPB => open ); end rtl;