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From: cvs at opencores.org<cvs@o...>
Date: Mon Oct 31 11:05:14 CET 2005
Subject: [cvs-checkins] MODIFIED: t48 ...
Date: 00/05/10 31:11:05 Added: t48/sw/verif/white_box/int_on_mb1 test.asm
Log:
initial check-in
Revision Changes Path
1.1 t48/sw/verif/white_box/int_on_mb1/test.asm
http://www.opencores.org/cvsweb.shtml/t48/sw/verif/white_box/int_on_mb1/test.asm?rev=1.1&content-type=text/x-cvsweb-markup
Index: test.asm
===================================================================
;; *******************************************************************
;; $Id: test.asm,v 1.1 2005/10/31 10:05:13 arniml Exp $
;;
;; Test interrupt on code in Program Memory Bank 1.
;; => Bug report "Problem with INT and JMP"
;; *******************************************************************
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
test_byte: equ 020h
ORG 0
;; Start of test
jmp start
;; interrupt hits djnz instruction with opcode 0EAh
;; bus conflict results on interrupt vector address 002h
;; -> retr instruction placed here, so test finds FAIL
retr
ORG 3
;; interrupt executed
mov r0, #test_byte
mov a, #0ffh
mov @r0, a
retr
start:
;; enable interrupt
en i
;; clear test byte
mov r1, #test_byte
clr a
mov @r1, a
call program_memory_bank_1
sel mb0
;; check if interrupt was successful
mov a, @r1
jz fail
pass: PASS
fail: FAIL
ORG 0800H
program_memory_bank_1:
;; spend some time and wait for interrupt
mov r2, #020h
djnz r2, $
ret
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