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From: cvs at opencores.org<cvs@o...>
Date: Thu Oct 27 19:21:35 CEST 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/10 27:19:21

Modified: or1k/rc203soc/syn/synplicity rc200.tcl
Log:
Supports two RAM banks by Jacob Bower


Revision Changes Path
1.2 or1k/rc203soc/syn/synplicity/rc200.tcl

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/syn/synplicity/rc200.tcl.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: rc200.tcl
===================================================================
RCS file: /cvsroot/jcastillo/or1k/rc203soc/syn/synplicity/rc200.tcl,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- rc200.tcl 18 Oct 2005 07:00:34 -0000 1.1
+++ rc200.tcl 27 Oct 2005 17:21:35 -0000 1.2
@@ -97,21 +97,21 @@
# Depending of cache size and register file type you must add or
# remove some of this files
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v"
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v"
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v"
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v"
-#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v"
+add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v"

# Top files
add_file "../../rtl/verilog/tc_top.v"