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From: cvs at opencores.org<cvs@o...>
Date: Thu Oct 27 19:20:52 CEST 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/10 27:19:20

Modified: or1k/rc203soc/rtl/verilog/or1200/rtl/verilog
or1200_defines.v
Log:
Supports two RAM banks by Jacob Bower


Revision Changes Path
1.3 or1k/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: or1200_defines.v
===================================================================
RCS file: /cvsroot/jcastillo/or1k/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- or1200_defines.v 18 Oct 2005 06:55:53 -0000 1.2
+++ or1200_defines.v 27 Oct 2005 17:20:51 -0000 1.3
@@ -44,6 +44,9 @@
// CVS Revision History
//
// $Log: or1200_defines.v,v $
+// Revision 1.3 2005/10/27 17:20:51 jcastillo
+// Supports two RAM banks by Jacob Bower
+//
// Revision 1.2 2005/10/18 06:55:53 jcastillo
// Added support for rc200 board by Jacob Bower
//
@@ -337,12 +340,12 @@
//
// Do not implement Data MMU
//
-`define OR1200_NO_DMMU
+//`define OR1200_NO_DMMU

//
// Do not implement Insn MMU
//
-`define OR1200_NO_IMMU
+//`define OR1200_NO_IMMU

//
// Select between ASIC and generic multiplier