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From: cvs at opencores.org<cvs@o...>
Date: Tue Oct 25 20:26:53 CEST 2005
Subject: [cvs-checkins] MODIFIED: single_port ...
Date: 00/05/10 25:20:26

Modified: single_port/VHDL single_port_pkg.vhd single_port.vhd
Log:
PAGENUM constant removed because the address bus width provides this information


Revision Changes Path
1.3 single_port/VHDL/single_port_pkg.vhd

http://www.opencores.org/cvsweb.shtml/single_port/VHDL/single_port_pkg.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: single_port_pkg.vhd
===================================================================
RCS file: /cvsroot/mgeng/single_port/VHDL/single_port_pkg.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- single_port_pkg.vhd 12 Oct 2005 19:39:27 -0000 1.2
+++ single_port_pkg.vhd 25 Oct 2005 18:26:52 -0000 1.3
@@ -47,6 +47,9 @@
-- CVS Revision History
--
-- $Log: single_port_pkg.vhd,v $
+-- Revision 1.3 2005/10/25 18:26:52 mgeng
+-- PAGENUM constant removed because the address bus width provides this information
+--
-- Revision 1.2 2005/10/12 19:39:27 mgeng
-- Buses unconstrained, LGPL header added
--
@@ -65,7 +68,6 @@

PACKAGE single_port_pkg IS
CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth
- CONSTANT PAGENUM : INTEGER := 4096; -- number of pages in memory.
-- Address bus type for internal memory
SUBTYPE addr_typ IS NATURAL;
-- Operations testbench can do.



1.3 single_port/VHDL/single_port.vhd

http://www.opencores.org/cvsweb.shtml/single_port/VHDL/single_port.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: single_port.vhd
===================================================================
RCS file: /cvsroot/mgeng/single_port/VHDL/single_port.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- single_port.vhd 12 Oct 2005 19:39:27 -0000 1.2
+++ single_port.vhd 25 Oct 2005 18:26:52 -0000 1.3
@@ -56,6 +56,9 @@
-- CVS Revision History
--
-- $Log: single_port.vhd,v $
+-- Revision 1.3 2005/10/25 18:26:52 mgeng
+-- PAGENUM constant removed because the address bus width provides this information
+--
-- Revision 1.2 2005/10/12 19:39:27 mgeng
-- Buses unconstrained, LGPL header added
--
@@ -89,7 +92,7 @@
BEGIN

mem_proc : PROCESS(d, a, rnw)
- TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF STD_LOGIC_VECTOR(d'RANGE);
+ TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF STD_LOGIC_VECTOR(d'RANGE);
VARIABLE mem : mem_typ;
BEGIN
IF ( rnw = '0') THEN -- Write
@@ -105,8 +108,8 @@
BEGIN

mem_proc : PROCESS(d, a, rnw)
- TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BIT_VECTOR(d'RANGE);
- TYPE flag_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BOOLEAN;
+ TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BIT_VECTOR(d'RANGE);
+ TYPE flag_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BOOLEAN;
VARIABLE mem : mem_typ;
VARIABLE flag : flag_typ;
BEGIN