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From: cvs at opencores.org<cvs@o...>
Date: Tue Oct 25 07:50:14 CEST 2005
Subject: [cvs-checkins] MODIFIED: risc16f84 ...
Date: 00/05/10 25:07:50

Modified: risc16f84 risc16f84_clk2x.v
Log:
Please update risc16f84_clk2x.v inside of b13c_environment.zip file to this latest version.


Revision Changes Path
1.3 risc16f84/risc16f84_clk2x.v

http://www.opencores.org/cvsweb.shtml/risc16f84/risc16f84_clk2x.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: risc16f84_clk2x.v
===================================================================
RCS file: /cvsroot/jclaytons/risc16f84/risc16f84_clk2x.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- risc16f84_clk2x.v 25 Oct 2005 05:39:08 -0000 1.2
+++ risc16f84_clk2x.v 25 Oct 2005 05:50:10 -0000 1.3
@@ -153,6 +153,7 @@
// Update: 10/24/05 Added code patches to fix interrupt bug and status flag updates
// when using literal value of 0x03. These bugs were reported by
// an opencores.org user. Added three "disable_status_x" signals.
+// Modified file still needs to be tested.
//
// Description
//---------------------------------------------------------------------------