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From: cvs at opencores.org<cvs@o...>
Date: Wed Oct 19 13:37:57 CEST 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/10 19:13:37

Modified: or1k/or1200/rtl/verilog or1200_defines.v
or1200_dpram_32x32.v or1200_du.v
or1200_spram_1024x32.v or1200_spram_1024x32_bw.v
or1200_spram_1024x8.v or1200_spram_128x32.v
or1200_spram_2048x32.v or1200_spram_2048x32_bw.v
or1200_spram_2048x8.v or1200_spram_256x21.v
or1200_spram_32x24.v or1200_spram_512x20.v
or1200_spram_64x14.v or1200_spram_64x22.v
or1200_spram_64x24.v or1200_tpram_32x32.v
Log:
Added support for RAMB16 Xilinx4/Spartan3 primitives




Revision Changes Path
1.44 or1k/or1200/rtl/verilog/or1200_defines.v

http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_defines.v.diff?r1=1.43&r2=1.44

(In the diff below, changes in quantity of whitespace are not shown.)

Index: or1200_defines.v
===================================================================
RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_defines.v,v
retrieving revision 1.43
retrieving revision 1.44
diff -u -b -r1.43 -r1.44
--- or1200_defines.v 7 Jan 2005 09:23:39 -0000 1.43
+++ or1200_defines.v 19 Oct 2005 11:37:56 -0000 1.44
@@ -44,6 +44,9 @@
// CVS Revision History
//
// $Log: or1200_defines.v,v $
+// Revision 1.44 2005/10/19 11:37:56 jcastillo
+// Added support for RAMB16 Xilinx4/Spartan3 primitives
+//
// Revision 1.43 2005/01/07 09:23:39 andreje
// l.ff1 and l.cmov instructions added
//
@@ -318,6 +321,7 @@
// Target FPGA memories
//
//`define OR1200_ALTERA_LPM
+//`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
@@ -574,7 +578,7 @@
// Type of register file RAM
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
-// `define OR1200_RFRAM_TWOPORT
+//`define OR1200_RFRAM_TWOPORT
//
// Memory macro dual port (see or1200_dpram_32x32.v)
//`define OR1200_RFRAM_DUALPORT
@@ -973,11 +977,7 @@
`define OR1200_DU_DVRDCR_PAIRS 8

// Define if you want trace buffer
-// (for now only available for Xilinx Virtex FPGAs)
-`ifdef OR1200_ASIC
-`else
//`define OR1200_DU_TB_IMPLEMENTED
-`endif

//
// Address offsets of DU registers inside DU group



1.10 or1k/or1200/rtl/verilog/or1200_dpram_32x32.v

http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_dpram_32x32.v.diff?r1=1.9&r2=1.10

(In the diff below, changes in quantity of whitespace are not shown.)

Index: or1200_dpram_32x32.v
===================================================================
RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_dpram_32x32.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- or1200_dpram_32x32.v 8 Jun 2004 18:15:48 -0000 1.9
+++ or1200_dpram_32x32.v 19 Oct 2005 11:37:56 -0000 1.10
@@ -21,7 +21,8 @@
//// - Virage 2-port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
-//// - Xilinx Virtex RAMB4_S16_S16 ////
+//// - Xilinx Virtex RAMB16 ////
+//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
@@ -62,6 +63,9 @@
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
+// Revision 1.10 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.9 2004/06/08 18:15:48 lampret // Changed behavior of the simulation generic models // @@ -414,6 +418,40 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +RAMB16_S36_S36 ramb16_s36_s36( + .CLKA(clk_a), + .SSRA(rst_a), + .ADDRA({4'b0000, addr_a}), + .DIA(32'h00000000), + .DIPA(4'h0), + .ENA(ce_a), + .WEA(1'b0), + .DOA(do_a), + .DOPA(), + + .CLKB(clk_b), + .SSRB(rst_b), + .ADDRB({4'b0000, addr_b}), + .DIB(di_b), + .DIPB(4'h0), + .ENB(ce_b), + .WEB(we_b), + .DOB(), + .DOPB() +); + +`else + `ifdef OR1200_ALTERA_LPM_XXX // @@ -504,7 +542,8 @@ mem[addr_b] <= #1 di_b; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_XILINX_RAM32X1D `endif // !OR1200_VIRTUALSILICON_SSP_T1 `endif // !OR1200_VIRTUALSILICON_SSP_T2 1.12 or1k/or1200/rtl/verilog/or1200_du.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_du.v.diff?r1=1.11&r2=1.12 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_du.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_du.v,v retrieving revision 1.11 retrieving revision 1.12 diff -u -b -r1.11 -r1.12 --- or1200_du.v 7 Jan 2005 09:35:08 -0000 1.11 +++ or1200_du.v 19 Oct 2005 11:37:56 -0000 1.12 @@ -44,6 +44,9 @@ // CVS Revision History // // $Log: or1200_du.v,v $ +// Revision 1.12 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.11 2005/01/07 09:35:08 andreje // du_hwbkpt disabled when debug unit not implemented // @@ -1700,151 +1703,74 @@ // // Trace buffer RAMs // -RAMB4_S16_S16 tbia_ramb4_s16_0( - .CLKA(clk), - .RSTA(rst), - .ADDRA(tb_wadr), - .DIA(spr_dat_npc[15:0]), - .ENA(1'b1), - .WEA(tb_enw), - .DOA(), - - .CLKB(clk), - .RSTB(rst), - .ADDRB(spr_addr[7:0]), - .DIB(16'h0000), - .ENB(1'b1), - .WEB(1'b0), - .DOB(tbia_dat_o[15:0]) -); - -RAMB4_S16_S16 tbia_ramb4_s16_1( - .CLKA(clk), - .RSTA(rst), - .ADDRA(tb_wadr), - .DIA(spr_dat_npc[31:16]), - .ENA(1'b1), - .WEA(tb_enw), - .DOA(), - - .CLKB(clk), - .RSTB(rst), - .ADDRB(spr_addr[7:0]), - .DIB(16'h0000), - .ENB(1'b1), - .WEB(1'b0), - .DOB(tbia_dat_o[31:16]) -); -RAMB4_S16_S16 tbim_ramb4_s16_0( - .CLKA(clk), - .RSTA(rst), - .ADDRA(tb_wadr), - .DIA(ex_insn[15:0]), - .ENA(1'b1), - .WEA(tb_enw), - .DOA(), - - .CLKB(clk), - .RSTB(rst), - .ADDRB(spr_addr[7:0]), - .DIB(16'h0000), - .ENB(1'b1), - .WEB(1'b0), - .DOB(tbim_dat_o[15:0]) -); - -RAMB4_S16_S16 tbim_ramb4_s16_1( - .CLKA(clk), - .RSTA(rst), - .ADDRA(tb_wadr), - .DIA(ex_insn[31:16]), - .ENA(1'b1), - .WEA(tb_enw), - .DOA(), - - .CLKB(clk), - .RSTB(rst), - .ADDRB(spr_addr[7:0]), - .DIB(16'h0000), - .ENB(1'b1), - .WEB(1'b0), - .DOB(tbim_dat_o[31:16]) -); +or1200_dpram_256x32 tbia_ram( + .clk_a(clk), + .rst_a(rst), + .addr_a(spr_addr[7:0]), + .ce_a(1'b1), + .oe_a(1'b1), + .do_a(tbia_dat_o), + + .clk_b(clk), + .rst_b(rst), + .addr_b(tb_wadr), + .di_b(spr_dat_npc), + .ce_b(1'b1), + .we_b(tb_enw) -RAMB4_S16_S16 tbar_ramb4_s16_0( - .CLKA(clk), - .RSTA(rst), - .ADDRA(tb_wadr), - .DIA(rf_dataw[15:0]), - .ENA(1'b1), - .WEA(tb_enw), - .DOA(), - - .CLKB(clk), - .RSTB(rst), - .ADDRB(spr_addr[7:0]), - .DIB(16'h0000), - .ENB(1'b1), - .WEB(1'b0), - .DOB(tbar_dat_o[15:0]) ); -RAMB4_S16_S16 tbar_ramb4_s16_1( - .CLKA(clk), - .RSTA(rst), - .ADDRA(tb_wadr), - .DIA(rf_dataw[31:16]), - .ENA(1'b1), - .WEA(tb_enw), - .DOA(), - - .CLKB(clk), - .RSTB(rst), - .ADDRB(spr_addr[7:0]), - .DIB(16'h0000), - .ENB(1'b1), - .WEB(1'b0), - .DOB(tbar_dat_o[31:16]) +or1200_dpram_256x32 tbim_ram( + .clk_a(clk), + .rst_a(rst), + .addr_a(spr_addr[7:0]), + .ce_a(1'b1), + .oe_a(1'b1), + .do_a(tbim_dat_o), + + .clk_b(clk), + .rst_b(rst), + .addr_b(tb_wadr), + .di_b(ex_insn), + .ce_b(1'b1), + .we_b(tb_enw) ); -RAMB4_S16_S16 tbts_ramb4_s16_0( - .CLKA(clk), - .RSTA(rst), - .ADDRA(tb_wadr), - .DIA(tb_timstmp[15:0]), - .ENA(1'b1), - .WEA(tb_enw), - .DOA(), - - .CLKB(clk), - .RSTB(rst), - .ADDRB(spr_addr[7:0]), - .DIB(16'h0000), - .ENB(1'b1), - .WEB(1'b0), - .DOB(tbts_dat_o[15:0]) +or1200_dpram_256x32 tbar_ram( + .clk_a(clk), + .rst_a(rst), + .addr_a(spr_addr[7:0]), + .ce_a(1'b1), + .oe_a(1'b1), + .do_a(tbar_dat_o), + + .clk_b(clk), + .rst_b(rst), + .addr_b(tb_wadr), + .di_b(rf_dataw), + .ce_b(1'b1), + .we_b(tb_enw) ); -RAMB4_S16_S16 tbts_ramb4_s16_1( - .CLKA(clk), - .RSTA(rst), - .ADDRA(tb_wadr), - .DIA(tb_timstmp[31:16]), - .ENA(1'b1), - .WEA(tb_enw), - .DOA(), - - .CLKB(clk), - .RSTB(rst), - .ADDRB(spr_addr[7:0]), - .DIB(16'h0000), - .ENB(1'b1), - .WEB(1'b0), - .DOB(tbts_dat_o[31:16]) +or1200_dpram_256x32 tbts_ram( + .clk_a(clk), + .rst_a(rst), + .addr_a(spr_addr[7:0]), + .ce_a(1'b1), + .oe_a(1'b1), + .do_a(tbts_dat_o), + + .clk_b(clk), + .rst_b(rst), + .addr_b(tb_wadr), + .di_b(tb_timstmp), + .ce_b(1'b1), + .we_b(tb_enw) ); `else + assign tbia_dat_o = 32'h0000_0000; assign tbim_dat_o = 32'h0000_0000; assign tbar_dat_o = 32'h0000_0000; 1.9 or1k/or1200/rtl/verilog/or1200_spram_1024x32.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_1024x32.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- or1200_spram_1024x32.v 8 Jun 2004 18:15:32 -0000 1.8 +++ or1200_spram_1024x32.v 19 Oct 2005 11:37:56 -0000 1.9 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_1024x32.v,v $ +// Revision 1.9 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.8 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -379,6 +383,78 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +// +// Block 0 +// +RAMB16_S9 ramb16_s9_0( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI(di[7:0]), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq[7:0]), + .DOP() +); + +// +// Block 1 +// +RAMB16_S9 ramb16_s9_1( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI(di[15:8]), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq[15:8]), + .DOP() +); + +// +// Block 2 +// +RAMB16_S9 ramb16_s9_2( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI(di[23:16]), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq[23:16]), + .DOP() +); + +// +// Block 3 +// +RAMB16_S9 ramb16_s9_3( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI(di[31:24]), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq[31:24]), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -446,7 +522,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.4 or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_1024x32_bw.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- or1200_spram_1024x32_bw.v 8 Jun 2004 18:15:32 -0000 1.3 +++ or1200_spram_1024x32_bw.v 19 Oct 2005 11:37:56 -0000 1.4 @@ -22,8 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// -//// - Altera LPM //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// //// //// To Do: //// //// - xilinx rams need external tri-state logic //// @@ -63,6 +63,9 @@ // CVS Revision History // // $Log: or1200_spram_1024x32_bw.v,v $ +// Revision 1.4 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.3 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -432,6 +435,78 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +// +// Block 0 +// +RAMB16_S9 ramb16_s9_0( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI(di[7:0]), + .DIP(1'b0), + .EN(ce), + .WE(we[0]), + .DO(doq[7:0]), + .DOP() +); + +// +// Block 1 +// +RAMB16_S9 ramb16_s9_1( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI(di[15:8]), + .DIP(1'b0), + .EN(ce), + .WE(we[1]), + .DO(doq[15:8]), + .DOP() +); + +// +// Block 2 +// +RAMB16_S9 ramb16_s9_2( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI(di[23:16]), + .DIP(1'b0), + .EN(ce), + .WE(we[2]), + .DO(doq[23:16]), + .DOP() +); + +// +// Block 3 +// +RAMB16_S9 ramb16_s9_3( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI(di[31:24]), + .DIP(1'b0), + .EN(ce), + .WE(we[3]), + .DO(doq[31:24]), + .DOP() +); + +`else + // // Generic single-port synchronous RAM model // @@ -488,7 +563,8 @@ mem_3[addr] <= #1 di[31:24]; -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.9 or1k/or1200/rtl/verilog/or1200_spram_1024x8.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_1024x8.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- or1200_spram_1024x8.v 8 Jun 2004 18:15:32 -0000 1.8 +++ or1200_spram_1024x8.v 19 Oct 2005 11:37:56 -0000 1.9 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_1024x8.v,v $ +// Revision 1.9 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.8 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -298,6 +302,30 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +RAMB16_S9 ramb16_s9( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI(di), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -365,7 +393,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.3 or1k/or1200/rtl/verilog/or1200_spram_128x32.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_128x32.v.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_128x32.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_128x32.v,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- or1200_spram_128x32.v 8 Jun 2004 18:15:32 -0000 1.2 +++ or1200_spram_128x32.v 19 Oct 2005 11:37:56 -0000 1.3 @@ -18,7 +18,8 @@ //// Supported ASIC RAMs are: //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// //// //// To Do: //// //// - add support for other RAM's //// @@ -59,6 +60,9 @@ // CVS Revision History // // $Log: or1200_spram_128x32.v,v $ +// Revision 1.3 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.2 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -214,16 +218,27 @@ `else -`ifdef OR1200_ALTERA_LPM +`ifdef OR1200_XILINX_RAMB16 // // Instantiation of FPGA memory: // -// Altera LPM +// Virtex4/Spartan3E // -// Added By Jamil Khatib +// Added By Nir Mor // +RAMB16_S36 ramb16_s36( + .CLK(clk), + .SSR(rst), + .ADDR({2'b00, addr}), + .DI(di), + .DIP(4'h0), + .EN(ce), + .WE(we), + .DO(doq), + .DOP() +); `else @@ -258,8 +273,8 @@ if (ce && we) mem[addr] <= #1 di; -`endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.10 or1k/or1200/rtl/verilog/or1200_spram_2048x32.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_2048x32.v.diff?r1=1.9&r2=1.10 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_2048x32.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_2048x32.v,v retrieving revision 1.9 retrieving revision 1.10 diff -u -b -r1.9 -r1.10 --- or1200_spram_2048x32.v 8 Jun 2004 18:15:32 -0000 1.9 +++ or1200_spram_2048x32.v 19 Oct 2005 11:37:56 -0000 1.10 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_2048x32.v,v $ +// Revision 1.10 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.9 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -483,6 +487,78 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +// +// Block 0 +// +RAMB16_S9 ramb16_s9_0( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI(di[7:0]), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq[7:0]), + .DOP() +); + +// +// Block 1 +// +RAMB16_S9 ramb16_s9_1( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI(di[15:8]), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq[15:8]), + .DOP() +); + +// +// Block 2 +// +RAMB16_S9 ramb16_s9_2( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI(di[23:16]), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq[23:16]), + .DOP() +); + +// +// Block 3 +// +RAMB16_S9 ramb16_s9_3( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI(di[31:24]), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq[31:24]), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -550,7 +626,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.5 or1k/or1200/rtl/verilog/or1200_spram_2048x32_bw.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_2048x32_bw.v.diff?r1=1.4&r2=1.5 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_2048x32_bw.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_2048x32_bw.v,v retrieving revision 1.4 retrieving revision 1.5 diff -u -b -r1.4 -r1.5 --- or1200_spram_2048x32_bw.v 8 Jun 2004 18:15:32 -0000 1.4 +++ or1200_spram_2048x32_bw.v 19 Oct 2005 11:37:56 -0000 1.5 @@ -22,8 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// -//// - Altera LPM //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// //// //// To Do: //// //// - xilinx rams need external tri-state logic //// @@ -63,6 +63,9 @@ // CVS Revision History // // $Log: or1200_spram_2048x32_bw.v,v $ +// Revision 1.5 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.4 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -536,6 +539,78 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +// +// Block 0 +// +RAMB16_S9 ramb16_s9_0( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI(di[7:0]), + .DIP(1'b0), + .EN(ce), + .WE(we[0]), + .DO(doq[7:0]), + .DOP() +); + +// +// Block 1 +// +RAMB16_S9 ramb16_s9_1( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI(di[15:8]), + .DIP(1'b0), + .EN(ce), + .WE(we[1]), + .DO(doq[15:8]), + .DOP() +); + +// +// Block 2 +// +RAMB16_S9 ramb16_s9_2( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI(di[23:16]), + .DIP(1'b0), + .EN(ce), + .WE(we[2]), + .DO(doq[23:16]), + .DOP() +); + +// +// Block 3 +// +RAMB16_S9 ramb16_s9_3( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI(di[31:24]), + .DIP(1'b0), + .EN(ce), + .WE(we[3]), + .DO(doq[31:24]), + .DOP() +); + +`else + // // Generic single-port synchronous RAM model // @@ -591,7 +666,8 @@ if (ce && we[3]) mem_3[addr] <= #1 di[31:24]; -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.9 or1k/or1200/rtl/verilog/or1200_spram_2048x8.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_2048x8.v.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_2048x8.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_2048x8.v,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- or1200_spram_2048x8.v 8 Jun 2004 18:15:32 -0000 1.8 +++ or1200_spram_2048x8.v 19 Oct 2005 11:37:56 -0000 1.9 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_2048x8.v,v $ +// Revision 1.9 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.8 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -324,6 +328,30 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +RAMB16_S9 ramb16_s9( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI(di), + .DIP(1'b0), + .EN(ce), + .WE(we), + .DO(doq), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -391,7 +419,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.9 or1k/or1200/rtl/verilog/or1200_spram_256x21.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_256x21.v.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_256x21.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_256x21.v,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- or1200_spram_256x21.v 8 Jun 2004 18:15:32 -0000 1.8 +++ or1200_spram_256x21.v 19 Oct 2005 11:37:56 -0000 1.9 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMBS16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_256x21.v,v $ +// Revision 1.9 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.8 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -154,7 +158,13 @@ // // Internal wires and registers // +`ifdef OR1200_XILINX_RAMB4 wire [10:0] unconnected; +`else +`ifdef OR1200_XILINX_RAMB16 +wire [10:0] unconnected; +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `ifdef OR1200_ARTISAN_SSP `else @@ -308,6 +318,30 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +RAMB16_S36 ramb16_s36( + .CLK(clk), + .SSR(rst), + .ADDR({1'b0,addr}), + .DI({11'b00000000000,di[20:0]}), + .DIP(4'h0), + .EN(ce), + .WE(we), + .DO({unconnected,doq[20:0]}), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -375,7 +409,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.3 or1k/or1200/rtl/verilog/or1200_spram_32x24.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_32x24.v.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_32x24.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_32x24.v,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- or1200_spram_32x24.v 8 Jun 2004 18:15:32 -0000 1.2 +++ or1200_spram_32x24.v 19 Oct 2005 11:37:56 -0000 1.3 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_32x24.v,v $ +// Revision 1.3 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.2 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -116,7 +120,13 @@ // // Internal wires and registers // +`ifdef OR1200_XILINX_RAMB4 wire [31:24] unconnected; +`else +`ifdef OR1200_XILINX_RAMB16 +wire [31:24] unconnected; +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `ifdef OR1200_ARTISAN_SSP `else @@ -221,6 +231,30 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +RAMB16_S36 ramb16_s36( + .CLK(clk), + .SSR(rst), + .ADDR({4'b0000, addr}), + .DI({8'h00, di}), + .DIP(4'h0), + .EN(ce), + .WE(we), + .DO({unconnected, doq}), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -266,7 +300,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.9 or1k/or1200/rtl/verilog/or1200_spram_512x20.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_512x20.v.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_512x20.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_512x20.v,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- or1200_spram_512x20.v 8 Jun 2004 18:15:32 -0000 1.8 +++ or1200_spram_512x20.v 19 Oct 2005 11:37:56 -0000 1.9 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_512x20.v,v $ +// Revision 1.9 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.8 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -151,7 +155,13 @@ // // Internal wires and registers // +`ifdef OR1200_XILINX_RAMB4 wire [3:0] unconnected; +`else +`ifdef OR1200_XILINX_RAMB16 +wire [11:0] unconnected; +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `ifdef OR1200_ARTISAN_SSP `else @@ -318,6 +328,30 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +RAMB16_S36 ramb16_s36( + .CLK(clk), + .SSR(rst), + .ADDR(addr), + .DI({12'h000,di}), + .DIP(4'h0), + .EN(ce), + .WE(we), + .DO({unconnected,doq}), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -385,7 +419,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.9 or1k/or1200/rtl/verilog/or1200_spram_64x14.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_64x14.v.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_64x14.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_64x14.v,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- or1200_spram_64x14.v 8 Jun 2004 18:15:32 -0000 1.8 +++ or1200_spram_64x14.v 19 Oct 2005 11:37:56 -0000 1.9 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_64x14.v,v $ +// Revision 1.9 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.8 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -145,7 +149,14 @@ // // Internal wires and registers // + +`ifdef OR1200_XILINX_RAMB4 +wire [1:0] unconnected; +`else +`ifdef OR1200_XILINX_RAMB16 wire [1:0] unconnected; +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `ifdef OR1200_ARTISAN_SSP `else @@ -278,7 +289,7 @@ .CLK(clk), .RST(rst), .ADDR({2'b00, addr}), - .DI({unconnected, di[13:0]}), + .DI({2'b00, di[13:0]}), .EN(ce), .WE(we), .DO({unconnected, doq[13:0]}) @@ -286,6 +297,28 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// + +RAMB16_S18 ramb16_s18( + .CLK(clk), + .SSR(rst), + .ADDR({4'b0000, addr}), + .DI({2'b00, di[13:0]}), + .DIP(2'b00), + .EN(ce), + .WE(we), + .DO({unconnected, doq[13:0]}), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -353,7 +386,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.9 or1k/or1200/rtl/verilog/or1200_spram_64x22.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_64x22.v.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_64x22.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_64x22.v,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- or1200_spram_64x22.v 8 Jun 2004 18:15:32 -0000 1.8 +++ or1200_spram_64x22.v 19 Oct 2005 11:37:56 -0000 1.9 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_64x22.v,v $ +// Revision 1.9 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.8 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -145,7 +149,14 @@ // // Internal wires and registers // +`ifdef OR1200_XILINX_RAMB4 wire [9:0] unconnected; +`else +`ifdef OR1200_XILINX_RAMB16 +wire [9:0] unconnected; +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 + `ifdef OR1200_ARTISAN_SSP `else @@ -291,7 +302,7 @@ .CLK(clk), .RST(rst), .ADDR({2'b00, addr}), - .DI({unconnected, di[21:16]}), + .DI({10'b0000000000, di[21:16]}), .EN(ce), .WE(we), .DO({unconnected, doq[21:16]}) @@ -299,6 +310,30 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +RAMB16_S36 ramb16_s36( + .CLK(clk), + .SSR(rst), + .ADDR({3'b000, addr}), + .DI({10'b0000000000,di}), + .DIP(4'h0), + .EN(ce), + .WE(we), + .DO({unconnected, doq}), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -366,7 +401,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.9 or1k/or1200/rtl/verilog/or1200_spram_64x24.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_spram_64x24.v.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_spram_64x24.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_spram_64x24.v,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- or1200_spram_64x24.v 8 Jun 2004 18:15:32 -0000 1.8 +++ or1200_spram_64x24.v 19 Oct 2005 11:37:56 -0000 1.9 @@ -22,7 +22,8 @@ //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -63,6 +64,9 @@ // CVS Revision History // // $Log: or1200_spram_64x24.v,v $ +// Revision 1.9 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.8 2004/06/08 18:15:32 lampret // Changed behavior of the simulation generic models // @@ -148,7 +152,13 @@ // // Internal wires and registers // +`ifdef OR1200_XILINX_RAMB4 wire [7:0] unconnected; +`else +`ifdef OR1200_XILINX_RAMB16 +wire [7:0] unconnected; +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `ifdef OR1200_ARTISAN_SSP `else @@ -294,7 +304,7 @@ .CLK(clk), .RST(rst), .ADDR({2'b00, addr}), - .DI({unconnected, di[23:16]}), + .DI({8'h00, di[23:16]}), .EN(ce), .WE(we), .DO({unconnected, doq[23:16]}) @@ -302,6 +312,30 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +RAMB16_S36 ramb16_s36( + .CLK(clk), + .SSR(rst), + .ADDR({3'b000, addr}), + .DI({8'h00,di}), + .DIP(4'h0), + .EN(ce), + .WE(we), + .DO({unconnected, doq}), + .DOP() +); + +`else + `ifdef OR1200_ALTERA_LPM // @@ -369,7 +403,8 @@ mem[addr] <= #1 di; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRTUALSILICON_SSP `endif // !OR1200_VIRAGE_SSP `endif // !OR1200_AVANT_ATP 1.5 or1k/or1200/rtl/verilog/or1200_tpram_32x32.v http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_tpram_32x32.v.diff?r1=1.4&r2=1.5 (In the diff below, changes in quantity of whitespace are not shown.) Index: or1200_tpram_32x32.v =================================================================== RCS file: /cvsroot/jcastillo/or1k/or1200/rtl/verilog/or1200_tpram_32x32.v,v retrieving revision 1.4 retrieving revision 1.5 diff -u -b -r1.4 -r1.5 --- or1200_tpram_32x32.v 8 Jun 2004 18:15:48 -0000 1.4 +++ or1200_tpram_32x32.v 19 Oct 2005 11:37:56 -0000 1.5 @@ -21,7 +21,8 @@ //// - Virage 2-port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16_S16 //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// //// - Altera LPM //// //// //// //// To Do: //// @@ -62,6 +63,9 @@ // CVS Revision History // // $Log: or1200_tpram_32x32.v,v $ +// Revision 1.5 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// // Revision 1.4 2004/06/08 18:15:48 lampret // Changed behavior of the simulation generic models // @@ -267,6 +271,40 @@ `else +`ifdef OR1200_XILINX_RAMB16 + +// +// Instantiation of FPGA memory: +// +// Virtex4/Spartan3E +// +// Added By Nir Mor +// + +RAMB16_S36_S36 ramb16_s36_s36( + .CLKA(clk_a), + .SSRA(rst_a), + .ADDRA({4'b0000,addr_a}), + .DIA(di_a), + .DIPA(4'h0), + .ENA(ce_a), + .WEA(we_a), + .DOA(do_a), + .DOPA(), + + .CLKB(clk_b), + .SSRB(rst_b), + .ADDRB({4'b0000,addr_b}), + .DIB(di_b), + .DIPB(4'h0), + .ENB(ce_b), + .WEB(we_b), + .DOB(do_b), + .DOPB() +); + +`else + `ifdef OR1200_ALTERA_LPM_XXX // @@ -375,7 +413,8 @@ addr_b_reg <= #1 addr_b; `endif // !OR1200_ALTERA_LPM -`endif // !OR1200_XILINX_RAMB4_S16_S16 +`endif // !OR1200_XILINX_RAMB16 +`endif // !OR1200_XILINX_RAMB4 `endif // !OR1200_VIRAGE_STP `endif // !OR1200_AVANT_ATP `endif // !OR1200_ARTISAN_SDP