Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Tue Oct 18 08:55:54 CEST 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/10 18:08:55

Modified: or1k/rc203soc/rtl/verilog/or1200/rtl/verilog
or1200_defines.v
Log:
Added support for rc200 board by Jacob Bower


Revision Changes Path
1.2 or1k/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: or1200_defines.v
===================================================================
RCS file: /cvsroot/jcastillo/or1k/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- or1200_defines.v 13 Dec 2004 17:15:47 -0000 1.1
+++ or1200_defines.v 18 Oct 2005 06:55:53 -0000 1.2
@@ -44,8 +44,11 @@
// CVS Revision History
//
// $Log: or1200_defines.v,v $
-// Revision 1.1 2004/12/13 17:15:47 jcastillo
-// Initial revision
+// Revision 1.2 2005/10/18 06:55:53 jcastillo
+// Added support for rc200 board by Jacob Bower
+//
+// Revision 1.1.1.1 2004/12/13 17:15:47 jcastillo
+// Firt import of OR1200 over Celoxica RC203 platform
//
// Revision 1.42 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
@@ -318,7 +321,7 @@
// Target FPGA memories
//
//`define OR1200_ALTERA_LPM
-`define OR1200_XILINX_RAMB
+`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
//