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From: cvs at opencores.org<cvs@o...>
Date: Fri Sep 30 18:10:50 CEST 2005
Subject: [cvs-checkins] MODIFIED: 395_vgs ...

Date: 00/05/09 30:18:10

Modified: 395_vgs/hdl gpuchip.ucf gpuchip.vhd sdramcntl.vhd xsasdramcntl.vhd Log: Blitter now mostly works! Revision Changes Path 1.4 395_vgs/hdl/gpuchip.ucf http://www.opencores.org/cvsweb.shtml/395_vgs/hdl/gpuchip.ucf.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: gpuchip.ucf =================================================================== RCS file: /cvsroot/zuofu/395_vgs/hdl/gpuchip.ucf,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- gpuchip.ucf 23 Sep 2005 01:33:29 -0000 1.3 +++ gpuchip.ucf 30 Sep 2005 16:10:47 -0000 1.4 @@ -6,6 +6,66 @@ # address bus # data bus # +#NET "pin_cwrite" LOC = "p59" ; +#NET "pin_cread" LOC = "p39" ; +#NET "pin_cAddr<0>" LOC = "p75" ; +#NET "pin_cAddr<10>" LOC = "p38" ; +#NET "pin_cAddr<11>" LOC = "p44" ; +#NET "pin_cAddr<12>" LOC = "p46" ; +#NET "pin_cAddr<13>" LOC = "p49" ; +#NET "pin_cAddr<14>" LOC = "p57" ; +#NET "pin_cAddr<1>" LOC = "p74" ; +#NET "pin_cAddr<2>" LOC = "p30" ; +#NET "pin_cAddr<3>" LOC = "p31" ; +#NET "pin_cAddr<4>" LOC = "p78" ; +#NET "pin_cAddr<5>" LOC = "p42" ; +#NET "pin_cAddr<6>" LOC = "p40" ; +#NET "pin_cAddr<7>" LOC = "p29" ; +#NET "pin_cAddr<8>" LOC = "p28" ; +#NET "pin_cAddr<9>" LOC = "p27" ; +#NET "pin_cread" LOC = "p39" ; +#NET "pin_cwrite" LOC = "p59" ; +#NET "pin_cAddr<0>" LOC = "p75" ; +#NET "pin_cAddr<10>" LOC = "p38" ; +#NET "pin_cAddr<11>" LOC = "p44" ; +#NET "pin_cAddr<12>" LOC = "p46" ; +#NET "pin_cAddr<13>" LOC = "p49" ; +#NET "pin_cAddr<14>" LOC = "p57" ; +#NET "pin_cAddr<1>" LOC = "p74" ; +#NET "pin_cAddr<2>" LOC = "p30" ; +#NET "pin_cAddr<3>" LOC = "p31" ; +#NET "pin_cAddr<4>" LOC = "p78" ; +#NET "pin_cAddr<5>" LOC = "p42" ; +#NET "pin_cAddr<6>" LOC = "p40" ; +#NET "pin_cAddr<7>" LOC = "p29" ; +#NET "pin_cAddr<8>" LOC = "p28" ; +#NET "pin_cAddr<9>" LOC = "p27" ; +#NET "pin_cData<0>" LOC = "p80" ; +#NET "pin_cData<10>" LOC = "p85" ; +#NET "pin_cData<11>" LOC = "p86" ; +#NET "pin_cData<12>" LOC = "p87" ; +#NET "pin_cData<13>" LOC = "p94" ; +#NET "pin_cData<14>" LOC = "p66" ; +#NET "pin_cData<15>" LOC = "p64" ; +#NET "pin_cData<1>" LOC = "p77" ; +#NET "pin_cData<2>" LOC = "p83" ; +#NET "pin_cData<3>" LOC = "p79" ; +#NET "pin_cData<4>" LOC = "p76" ; +#NET "pin_cData<5>" LOC = "p56" ; +#NET "pin_cData<6>" LOC = "p54" ; +#NET "pin_cData<7>" LOC = "p62" ; +#NET "pin_cData<8>" LOC = "p67" ; +#NET "pin_cData<9>" LOC = "p84" ; +#NET "pin_cData<0>" LOC = "p80" ; +#NET "pin_cData<1>" LOC = "p77" ; +#NET "pin_cData<2>" LOC = "p83" ; +#NET "pin_cData<3>" LOC = "p79" ; +#NET "pin_cData<4>" LOC = "p76" ; +#NET "pin_cData<5>" LOC = "p56" ; +#NET "pin_cData<6>" LOC = "p54" ; +#NET "pin_cData<7>" LOC = "p62" ; +#NET "pin_SRCce" LOC = "p60" ; + #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments @@ -13,44 +73,11 @@ NET "pin_ba<1>" LOC = "p137" ; NET "pin_blue<0>" LOC = "p21" ; NET "pin_blue<1>" LOC = "p22" ; -NET "pin_cAddr<0>" LOC = "p75" ; -NET "pin_cAddr<10>" LOC = "p38" ; -NET "pin_cAddr<11>" LOC = "p44" ; -NET "pin_cAddr<12>" LOC = "p46" ; -NET "pin_cAddr<13>" LOC = "p49" ; -NET "pin_cAddr<14>" LOC = "p57" ; -NET "pin_cAddr<1>" LOC = "p74" ; -NET "pin_cAddr<2>" LOC = "p30" ; -NET "pin_cAddr<3>" LOC = "p31" ; -NET "pin_cAddr<4>" LOC = "p78" ; -NET "pin_cAddr<5>" LOC = "p42" ; -NET "pin_cAddr<6>" LOC = "p40" ; -NET "pin_cAddr<7>" LOC = "p29" ; -NET "pin_cAddr<8>" LOC = "p28" ; -NET "pin_cAddr<9>" LOC = "p27" ; NET "pin_cas_n" LOC = "p126" ; -NET "pin_cData<0>" LOC = "p80" ; -NET "pin_cData<10>" LOC = "p85" ; -NET "pin_cData<11>" LOC = "p86" ; -NET "pin_cData<12>" LOC = "p87" ; -NET "pin_cData<13>" LOC = "p94" ; -NET "pin_cData<14>" LOC = "p66" ; -NET "pin_cData<15>" LOC = "p64" ; -NET "pin_cData<1>" LOC = "p77" ; -NET "pin_cData<2>" LOC = "p83" ; -NET "pin_cData<3>" LOC = "p79" ; -NET "pin_cData<4>" LOC = "p76" ; -NET "pin_cData<5>" LOC = "p56" ; -NET "pin_cData<6>" LOC = "p54" ; -NET "pin_cData<7>" LOC = "p62" ; -NET "pin_cData<8>" LOC = "p67" ; -NET "pin_cData<9>" LOC = "p84" ; NET "pin_ce_n" LOC = "p41" ; NET "pin_cke" LOC = "p131" ; NET "pin_clkin" LOC = "p88" ; -NET "pin_cread" LOC = "p39" ; NET "pin_cs_n" LOC = "p132" ; -NET "pin_cwrite" LOC = "p59" ; NET "pin_dqmh" LOC = "p124" ; NET "pin_dqml" LOC = "p122" ; NET "pin_green<0>" LOC = "p19" ; @@ -93,35 +120,6 @@ NET "pin_vsync_n" LOC = "p26" ; NET "pin_we_n" LOC = "p123" ; -NET "pin_cAddr<0>" LOC = "p75" ; -NET "pin_cAddr<10>" LOC = "p38" ; -NET "pin_cAddr<11>" LOC = "p44" ; -NET "pin_cAddr<12>" LOC = "p46" ; -NET "pin_cAddr<13>" LOC = "p49" ; -NET "pin_cAddr<14>" LOC = "p57" ; -NET "pin_cAddr<1>" LOC = "p74" ; -NET "pin_cAddr<2>" LOC = "p30" ; -NET "pin_cAddr<3>" LOC = "p31" ; -NET "pin_cAddr<4>" LOC = "p78" ; -NET "pin_cAddr<5>" LOC = "p42" ; -NET "pin_cAddr<6>" LOC = "p40" ; -NET "pin_cAddr<7>" LOC = "p29" ; -NET "pin_cAddr<8>" LOC = "p28" ; -NET "pin_cAddr<9>" LOC = "p27" ; - -NET "pin_cData<0>" LOC = "p80" ; -NET "pin_cData<1>" LOC = "p77" ; -NET "pin_cData<2>" LOC = "p83" ; -NET "pin_cData<3>" LOC = "p79" ; -NET "pin_cData<4>" LOC = "p76" ; -NET "pin_cData<5>" LOC = "p56" ; -NET "pin_cData<6>" LOC = "p54" ; -NET "pin_cData<7>" LOC = "p62" ; - -NET "pin_cread" LOC = "p39" ; -NET "pin_cwrite" LOC = "p59" ; -NET "pin_SRCce" LOC = "p60" ; - #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints 1.10 395_vgs/hdl/gpuchip.vhd http://www.opencores.org/cvsweb.shtml/395_vgs/hdl/gpuchip.vhd.diff?r1=1.9&r2=1.10 (In the diff below, changes in quantity of whitespace are not shown.) Index: gpuchip.vhd =================================================================== RCS file: /cvsroot/zuofu/395_vgs/hdl/gpuchip.vhd,v retrieving revision 1.9 retrieving revision 1.10 diff -u -b -r1.9 -r1.10 --- gpuchip.vhd 23 Sep 2005 22:05:55 -0000 1.9 +++ gpuchip.vhd 30 Sep 2005 16:10:47 -0000 1.10 @@ -29,7 +29,7 @@ use WORK.xsasdram.all; use WORK.sdram.all; use WORK.vga_pckg.all; -use WORK.gpu_core_pckg.all; +use WORK.blitter_pckg.all; entity gpuChip is @@ -49,7 +49,7 @@ PIXELS_PER_LINE : natural := 320; -- width of image in pixels LINES_PER_FRAME : natural := 240; -- height of image in scanlines FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x - PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111100001111" + PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111111111111" ); port( @@ -64,12 +64,6 @@ pin_hsync_n : out std_logic; pin_vsync_n : out std_logic; - -- SRAM Cache connections - --pin_cData : inout std_logic_vector(15 downto 0); -- data bus to Cache - --pin_cAddr : out std_logic_vector(14 downto 0); -- Cache address bus - --pin_cwrite : out std_logic; - --pin_cread : out std_logic; - -- SDRAM pin connections pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays pin_sclk : out std_logic; -- clock to SDRAM @@ -93,14 +87,43 @@ constant HI: std_logic := '1'; constant LO: std_logic := '0'; + type gpuState is ( + INIT, -- init + INIT_BKG, + DRAW_BKG, + BLIT_REST, + INIT_SPRITE, + DRAW_SPRITE, + UPDATE + ); + + signal state_r, state_x : gpuState; -- state register and next state + + --registers + signal plane0_dest_r, plane0_dest_x : std_logic_vector (ADDR_WIDTH - 1 downto 0); -- sprite dest register + signal plane0_ypos_r, plane0_ypos_x : std_logic_vector (11 downto 0); + signal delay_r, delay_x : std_logic_vector (19 downto 0); --20 bit counter for delay + signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0); + signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0); + signal line_size_x, line_size_r : std_logic_vector (11 downto 0); + signal source_lines_x, source_lines_r : std_logic_vector (15 downto 0); + signal alphaOp_x, alphaOp_r : std_logic; + signal front_buffer_x, front_buffer_r : std_logic; + --internal signals - signal sysClk : std_logic; -- system clock signal sysReset : std_logic; -- system reset + signal blit_reset : std_logic; + signal reset_blitter : std_logic; - signal start_read : std_logic; + -- Blitter signals + signal blit_begin : std_logic; signal source_address : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal source_lines : std_logic_vector (15 downto 0); + signal line_size : std_logic_vector (11 downto 0); signal target_address : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal end_address : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal blit_done : std_logic; + signal alphaOp : std_logic; + signal front_buffer : std_logic; --Application Side Signals for the DualPort Controller signal rst_i : std_logic; --tied reset signal @@ -191,6 +214,7 @@ hDIn1 => hDIn1, hDOut1 => hDOut1, status1 => open, + -- connections to the SDRAM controller rst => sdram_rst, rd => sdram_rd, @@ -259,7 +283,7 @@ ); ------------------------------------------------------------------------------------------------------------ --- instance of vga +-- Instance of VGA driver, this unit generates the video signals from VRAM ------------------------------------------------------------------------------------------------------------ @@ -288,56 +312,38 @@ blank => open ); - ------------------------------------------------------------------------------------------------------------ --- instance of fill-unit +-- instance of main blitter ------------------------------------------------------------------------------------------------------------ --- u4: fillunit --- generic map( --- FREQ => FREQ, --- DATA_WIDTH => DATA_WIDTH, --- HADDR_WIDTH => ADDR_WIDTH --- ) --- port map( --- clk => sdram_clk1x, -- master clock --- reset => sysReset, -- reset for this entity --- rd1 => rd1, -- initiate read operation --- wr1 => wr1, -- initiate write operation --- opBegun => opBegun1, --operation recieved --- done1 => done1, -- read or write operation is done --- hAddr1 => hAddr1, -- address to SDRAM --- hDIn1 => hDIn1, -- data to dualport to SDRAM --- hDOut1 => hDOut1 -- data from dualport to SDRAM --- ); --- - - u5: gpu_core + u4: Blitter generic map( FREQ => FREQ, + PIPE_EN => PIPE_EN, DATA_WIDTH => DATA_WIDTH, - HADDR_WIDTH => ADDR_WIDTH + ADDR_WIDTH => ADDR_WIDTH ) port map ( clk =>sdram_clk1x, - rst =>sysReset, - rd1 =>rd1, - wr1 =>wr1, - opBegun1 =>opBegun1, - done1 =>done1, - rddone1 =>rddone1, - rdPending1 =>rdPending1, - start_read =>start_read, + rst =>blit_reset, + rd =>rd1, + wr =>wr1, + opBegun =>opBegun1, + earlyopBegun =>earlyOpBegun1, + done =>done1, + rddone =>rddone1, + rdPending =>rdPending1, + Addr =>hAddr1, + DIn =>hDIn1, + DOut =>hDOut1, + blit_begin =>blit_begin, source_address =>source_address, + source_lines =>source_lines, target_address =>target_address, - end_address =>end_address, - hAddr1 =>hAddr1, - hDIn1 =>hDIn1, - hDOut1 =>hDOut1 - --CacheDIn =>pin_cData, - --CacheAddr =>pin_cAddr, - --cread =>pin_cread, - --cwrite =>pin_cwrite + line_size =>line_size, + alphaOp =>alphaOp, + blit_done =>blit_done, + front_buffer =>front_buffer ); -------------------------------------------------------------------------------------------------------------- @@ -345,30 +351,143 @@ -------------------------------------------------------------------------------------------------------------- -- Begin Top Level Module --- connect internal signals + -- connect internal signals rst_i <= sysReset; pin_ce_n <= '1'; -- disable Flash RAM + rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port) wr0 <= '0'; hAddr0 <= std_logic_vector(vga_address); - -- Port0 is reserved for VGA + blit_reset <= rst_i or reset_blitter; + -- Port0 is reserved for VGA pixels <= hDOut0 when drawframe = '1' else "0000000000000000"; + source_address <= source_address_r; + line_size <= line_size_r; + target_address <= target_address_r; + source_lines <= source_lines_r; + alphaOp <= alphaOp_r; + front_buffer <= YES;--front_buffer_r; + + comb:process(state_r, delay_r, plane0_dest_r) + begin + blit_begin <= NO; --default operations + reset_blitter <= NO; + + state_x <= state_r; --default register values + delay_x <= delay_r + 1; + source_address_x <= source_address_r; + line_size_x <= line_size_r; + target_address_x <= target_address_r; + source_lines_x <= source_lines_r; + alphaOp_x <= alphaOp_r; + plane0_dest_x <= plane0_dest_r; + plane0_ypos_x <= plane0_ypos_r; + front_buffer_x <= front_buffer_r; + + case state_r is + when INIT => + blit_begin <= NO; + reset_blitter <= YES; + state_x <= INIT_BKG; + plane0_dest_x <= x"000060"; + plane0_ypos_x <= x"000"; + front_buffer_x <= YES; + + when INIT_BKG => + --flip buffers + source_address_x <= x"012C00"; + line_size_x <= x"0A0"; + target_address_x <= x"000000"; + source_lines_x <= x"00EF"; + alphaOp_x <= NO; + blit_begin <= YES; + state_x <= DRAW_BKG; + + when DRAW_BKG => + blit_begin <= YES; + + if (blit_done = YES) then + reset_blitter <= YES; + state_x <= BLIT_REST; + end if; + + when BLIT_REST => + source_address_x <= x"01EBE5"; + line_size_x <= x"024"; + target_address_x <= plane0_dest_r; + source_lines_x <= x"004E"; + alphaOp_x <= YES; + + reset_blitter <= YES; + state_x <= INIT_SPRITE; + + when INIT_SPRITE => + blit_begin <= YES; + + state_x <= DRAW_SPRITE; + + when DRAW_SPRITE => + blit_begin <= YES; + + if (blit_done = YES) then + reset_blitter <= YES; + state_x <= UPDATE; + end if; + + when UPDATE => + reset_blitter <= YES; + if (delay_r = x"FFFFF") then + plane0_dest_x <= plane0_dest_r + x"000140"; + plane0_ypos_x <= plane0_ypos_r + x"001"; + if (plane0_ypos_r = x"050") then + plane0_dest_x <= x"000060"; + plane0_ypos_x <= x"000"; + end if; + state_x <= INIT_BKG; + end if; + + end case; + end process; + -- update the SDRAM address counter process(sdram_clk1x) begin if rising_edge(sdram_clk1x) then + + --VGA Related Stuff if eof = YES then drawframe <= not drawframe; -- draw every other frame - vga_address <= "00000000000000000000000"; -- reset the address at the end of a video frame - elsif earlyOpBegun0 = YES then + + -- reset the address at the end of a video frame depending on which buffer is the front + if (front_buffer = YES) then + vga_address <= x"000000"; + else + vga_address <= x"009600"; + end if; + elsif (earlyOpBegun0 = YES) then vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun - elsif drawframe = '0' then - vga_address <= vga_address + 1; --if we're not drawing a frame, keep incrementing the address end if; + + --reset stuff + if (sysReset = YES) then + state_r <= INIT; + end if; + + state_r <= state_x; + delay_r <= delay_x; + source_address_r <= source_address_x; + line_size_r <= line_size_x; + target_address_r <= target_address_x; + source_lines_r <= source_lines_x; + alphaOp_r <= alphaOp_x; + plane0_dest_r <= plane0_dest_x; + plane0_ypos_r <= plane0_ypos_x; + front_buffer_r <= front_buffer_x; + end if; end process; @@ -384,6 +503,4 @@ end if; end if; end process; - - end arch; \ No newline at end of file 1.2 395_vgs/hdl/sdramcntl.vhd http://www.opencores.org/cvsweb.shtml/395_vgs/hdl/sdramcntl.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: sdramcntl.vhd =================================================================== RCS file: /cvsroot/zuofu/395_vgs/hdl/sdramcntl.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- sdramcntl.vhd 11 Sep 2005 10:29:50 -0000 1.1 +++ sdramcntl.vhd 30 Sep 2005 16:10:47 -0000 1.2 @@ -333,7 +333,8 @@ combinatorial : process(rd, wr, hAddr, hDIn, hDOut_r, sDIn, state_r, opBegun_x, activeFlag_r, activeRow_r, rdPipeline_r, wrPipeline_r, hDOutOppPhase_r, nopCntr_r, lock, rfshCntr_r, timer_r, rasTimer_r, - wrTimer_r, refTimer_r, cmd_r, cke_r) + wrTimer_r, refTimer_r, cmd_r, cke_r, activeBank_r, ba_r) -- last 3 signals added + -- by Eric begin ----------------------------------------------------------- 1.2 395_vgs/hdl/xsasdramcntl.vhd http://www.opencores.org/cvsweb.shtml/395_vgs/hdl/xsasdramcntl.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: xsasdramcntl.vhd =================================================================== RCS file: /cvsroot/zuofu/395_vgs/hdl/xsasdramcntl.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- xsasdramcntl.vhd 11 Sep 2005 10:29:51 -0000 1.1 +++ xsasdramcntl.vhd 30 Sep 2005 16:10:47 -0000 1.2 @@ -99,9 +99,9 @@ generic( FREQ : natural := 50_000; -- operating frequency in KHz CLK_DIV : real := 1.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) - PIPE_EN : boolean := false; -- if true, enable pipelined read operations + PIPE_EN : boolean := true; -- if true, enable pipelined read operations MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh - MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank + MULTIPLE_ACTIVE_ROWS : boolean := true; -- if true, allow an active row in each bank DATA_WIDTH : natural := 16; -- host & SDRAM data width NROWS : natural := 4096; -- number of rows in SDRAM array NCOLS : natural := 512; -- number of columns in SDRAM array