LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
    •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us

    •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
    •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
    •  
    Navigation: All forums > Cvs-checkins > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: OpenCores CVS Agent<cvs@o...>
    Date: Sun Jan 30 21:41:45 CET 2005
    Subject: [cvs-checkins] MODIFIED: risc5x ...
    Top
    Date: 00/05/01 30:21:41

    Added: risc5x/hex_conv hex_conv.cpp hex_conv.exe jumptest.asm
    jumptest.hex jumptest.ucf readme.txt
    Log:



    Revision Changes Path
    1.1 risc5x/hex_conv/hex_conv.cpp

    http://www.opencores.org/cvsweb.shtml/risc5x/hex_conv/hex_conv.cpp?rev=1.1&content-type=text/x-cvsweb-markup

    Index: hex_conv.cpp
    ===================================================================
    //
    // Risc5x
    // www.OpenCores.Org - November 2001
    //
    //
    // This library is free software; you can distribute it and/or modify it
    // under the terms of the GNU Lesser General Public License as published
    // by the Free Software Foundation; either version 2.1 of the License, or
    // (at your option) any later version.
    //
    // This library is distributed in the hope that it will be useful, but
    // WITHOUT ANY WARRANTY; without even the implied warranty of
    // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    // See the GNU Lesser General Public License for more details.
    //
    // A RISC CPU core.
    //
    // (c) Mike Johnson 2001. All Rights Reserved.
    // mikej@o... for support or any other issues.
    //
    // Revision list
    //
    // version 1.0 initial opencores release
    //

    #include <stdio.h>
    #include <stdlib.h>

    #include <iostream>
    #include <fstream>
    #include <list>
    #include <vector>
    #include <string>
    using namespace std;

    #define ROM_SIZE 0x800

    class cLine
    {
    string line;
    public:

    typedef std::vector<cLine> List;
    cLine(string l) : line(l) {}
    string get() {return line;}
    };

    int hex_to_int(string hex, int start, int len)
    {
    int result = 0;

    for (int i = start; i < (start + len); i++) {
    result <<= 4;
    if (hex[i] >= '0' && hex[i] <= '9')
    result += (hex[i] - '0');
    else if (hex[i] >= 'A' && hex[i] <= 'F')
    result += (hex[i] - 'A') +10;
    else if (hex[i] >= 'a' && hex[i] <= 'f')
    result += (hex[i] - 'a') +10;
    else
    {
    printf("hex to int error \n");
    exit (1);
    }
    }
    return result;
    }

    int main(int argc, char* argv[])

    {
    // read file
    cLine::List l;
    string buffer;
    ifstream infile;

    if(argc != 2)
    {
    printf("no input file \n");
    return -1;
    }

    infile.open(argv[1]);
    if(infile.fail()) {
    printf("Could not open input file \n");
    return -1;
    }
    do { std::getline(infile,buffer,infile.widen('\n')); if(!buffer.empty()) { string::size_type sz1 = buffer.find(":"); if(sz1 != string::npos) { sz1+=1; string::size_type sz2 = buffer.find(";"); string real(&buffer[sz1]); l.push_back(cLine(real)); } } } while(!infile.fail()); infile.close(); // process int mem[ROM_SIZE]; string line; int len = l.size(); int i,j,k,sum; int wc,type,data; int file_addr = 0; int addr = 0; int offset = 0; int mask = 0; // clear mem for (i = 0; i < ROM_SIZE; i++) mem[i] = 0; // process file for (j = 0; j < len-1; j++) { line = l[j].get(); wc = hex_to_int(line,0,2); file_addr = hex_to_int(line,2,4); type = hex_to_int(line,6,2); sum = 0; for (i = 0; i < wc*2 + 9; i +=2) { sum += hex_to_int(line,i,2); } if ((sum & 0xff) != 0) printf("incorrect checksum line %d \n", j+1); int value = 0; if (type == 0) { for (i = 0; i < wc*2; i +=4) { value = hex_to_int(line,i + 8,2) + hex_to_int(line,i+10,2) * 256; mem[addr] = value; addr ++; } } } // print attribute statements /* for (k = 0; k < 6; k ++){ mask = 0x3 << (k*2); printf("\n\n"); for (j = 0; j < (ROM_SIZE/128); j++) { printf("attribute INIT_%02X of inst%d : label is \042",j,k); for (i = 0; i < 128; i+=4) { data = ((mem[(j*128) + (127 - i)] & mask) >> k*2); data <<= 2; data += ((mem[(j*128) + (126 - i)] & mask) >> k*2); data <<= 2; data += ((mem[(j*128) + (125 - i)] & mask) >> k*2); data <<= 2; data += ((mem[(j*128) + (124 - i)] & mask) >> k*2); printf("%02X",data); } printf("\042;\n"); } } */ // print ucf statements for (k = 0; k < 6; k ++){ mask = 0x3 << (k*2); printf("\n\n"); for (j = 0; j < (ROM_SIZE/128); j++) { printf("INST PRAMS_%d_INST INIT_%02X = ",k,j); for (i = 0; i < 128; i+=4) { data = ((mem[(j*128) + (127 - i)] & mask) >> k*2); data <<= 2; data += ((mem[(j*128) + (126 - i)] & mask) >> k*2); data <<= 2; data += ((mem[(j*128) + (125 - i)] & mask) >> k*2); data <<= 2; data += ((mem[(j*128) + (124 - i)] & mask) >> k*2); printf("%02X",data); } printf(";\n"); } } return 0; } 1.1 risc5x/hex_conv/hex_conv.exe http://www.opencores.org/cvsweb.shtml/risc5x/hex_conv/hex_conv.exe?rev=1.1&content-type=text/x-cvsweb-markup <<Binary file>> 1.1 risc5x/hex_conv/jumptest.asm http://www.opencores.org/cvsweb.shtml/risc5x/hex_conv/jumptest.asm?rev=1.1&content-type=text/x-cvsweb-markup Index: jumptest.asm =================================================================== ; LIST p=16C58 ; PIC16C58 is the target processor ; ; Core Sanity Test ; ; JUMPTEST.ASM ; ; test some jumps ; NEW in rev 1.1, test indirect addressing ; test some inc & decs ; sit in loop multiplying port A with a constant ; output 16 bit result on ports C & B ; CARRY equ H'00' ; Carry bit in STATUS register DC equ H'01' ; DC bit in STATUS register ZERO equ H'02' ; Zero bit in STATUS register W equ H'00' ; W indicator for many instruction (not the address!) INDF equ H'00' ; Magic register that uses INDIRECT register TIMER0 equ H'01' ; Timer register PC equ H'02' ; PC STATUS equ H'03' ; STATUS register F3 FSR equ H'04' ; INDIRECT Pointer Register porta equ H'05' ; I/O register F5 portb equ H'06' ; I/O register F6 portc equ H'07' ; I/O register F7 x equ H'09' ; scratch y equ H'0A' ; scratch rh equ H'0B' ; result h rl equ H'0C' ; result l mult MACRO bit btfsc y,bit addwf rh,1 rrf rh,1 rrf rl,1 ENDM start: movlw H'ff' tris porta ; PORTA is Input clrw tris portb ; PORTB is Output tris portc ; PORTC is Output movwf portb ; PORTB <= 00 movlw h'0B' movwf PC ; move to pc (jump1) movlw h'F0' ; fail 0 movwf portb goto fail jump1: movlw h'05' addwf PC,f ; jump forward to jump2 movlw h'F1' ; fail 1 movwf portb goto fail jump3: goto jump4 ; continue nop jump2: movlw h'04' subwf PC, f ; jump back to jump 3 movlw h'F2' ; fail 2 movwf portb goto fail jump4: movlw h'10' ; set locations 10-1F to xFF movwf FSR movlw h'ff' clrlp: movwf INDF incf FSR,F btfsc FSR,4 goto clrlp movlw h'10' movwf x movlw h'20' movwf y movlw x movwf FSR ; point FSR at x movf FSR,w xorlw h'89' ; check its x (note bit 7 set always) btfss STATUS,ZERO goto fail movf INDF,w xorlw h'10' ; check its 10 btfss STATUS,ZERO goto fail movlw h'15' ; write 15 to x using INDF movwf INDF movf x,w ; read x xorlw h'15' ; check its 15 btfss STATUS,ZERO goto fail incf FSR,F movf INDF,w xorlw h'20' ; check its 20 btfss STATUS,ZERO goto fail movlw h'00' movwf FSR movlw h'A5' ; paranoid ! movf INDF,w ; reading INDR itself should = 0 xorlw h'00' ; check btfss STATUS,ZERO goto fail ; check banking ; locations 20-2F, 40-4F, 60-6F all map to 0-0F ; locations 10-1F, 30-3F, 50-5F, 70-7F are real movlw h'00' movwf FSR ; set bank 0 movlw h'1F' movwf h'1F' movlw h'20' movwf FSR ; set bank 1 movlw h'3F' movwf h'1F' movlw h'40' movwf FSR ; set bank 2 movlw h'5F' movwf h'1F' movlw h'60' movwf FSR ; set bank 3 movlw h'7F' movwf h'1F' ; check movlw h'00' movwf FSR ; set bank 0 movf h'1F',w xorlw h'1F' btfss STATUS,ZERO goto fail movlw h'20' movwf FSR ; set bank 1 movf h'1F',w xorlw h'3F' btfss STATUS,ZERO goto fail movlw h'40' movwf FSR ; set bank 2 movf h'1F',w xorlw h'5F' btfss STATUS,ZERO goto fail movlw h'60' movwf FSR ; set bank 3 movf h'1F',w xorlw h'7F' btfss STATUS,ZERO goto fail movlw h'00' movwf FSR ; set bank 0 movlw h'45' movwf h'0F' movlw h'60' movwf FSR ; set bank 3 movlw h'54' movwf h'0F' movlw h'40' movwf FSR ; set bank 2 movf h'0f',w ; w should contain 54 xorlw h'54' btfsc STATUS,ZERO goto test1 movlw h'F3' ; fail 3 movwf portb goto fail test1: movlw h'00' movwf FSR ; set bank 0 movlw h'04' ; w <= 04 movwf x decf x,f ; x <= 03 decf x,f ; x <= 02 decf x,f ; x <= 01 decf x,f ; x <= 00 decf x,f ; x <= FF movf x,w xorlw h'FF' ; does w = ff ? btfss STATUS,ZERO ; skip if clear goto fail incf x,f ; x <= 00 incf x,f ; x <= 01 movf x,w xorlw h'01' ; does w = 01 btfss STATUS,ZERO goto fail ; test logic clrf x ; x <= 00 movlw h'a5' iorwf x,f ; x <= a5 swapf x,f ; x <= 5a movlw h'f0' andwf x,f ; x <= 50 comf x,f ; x <= af movlw h'5a' xorwf x,f ; x <= f5 ;check movfw x xorlw h'f5' btfsc STATUS,ZERO goto test2 movlw h'F4' ; fail 4 movwf portb goto fail test2: movlw h'23' movwf x ; x <= 23 movlw h'e1' ; w <= e1 addwf x,f ; x <= 04 btfss STATUS,CARRY goto fail ; carry should be set movlw h'02' ; w <= 02 subwf x,f ; x <= 02 btfss STATUS,CARRY goto fail ; borrow should be clear movlw h'34' ; w <= 34 subwf x,f ; x <= ce btfsc STATUS,CARRY goto fail ; borrow should be set movf x,w xorlw h'CE' btfss STATUS,ZERO goto fail ; x /= ce test3: movlw h'34' ; test dc flag movwf x movlw h'0F' addwf x,f ; x <= 43 btfsc STATUS,CARRY goto fail ; carry should be clear btfss STATUS,DC goto fail ; dc should be set movlw h'01' subwf x,f ; x <= 42 btfss STATUS,CARRY goto fail ; borrow should be clear btfss STATUS,DC goto fail ; dc borrow should be clear movlw h'FF' subwf x,f btfsc STATUS,CARRY goto fail ; borrow should be set btfsc STATUS,DC goto fail ; dc borrow should be set movf x,w xorlw h'43' ; final check btfss STATUS,ZERO goto fail ; x /= 43 movlw h'E0' ; ok movwf portb loop1: ; mult x by y movf porta,W movwf x movlw h'23' movwf y clrf rh clrf rl movf x,w bcf STATUS,CARRY mult 0 mult 1 mult 2 mult 3 mult 4 mult 5 mult 6 mult 7 movf rl,w movwf portb ; on port b low result movf rh,w movwf portc ; on port c high result goto loop1 fail: goto fail end 1.1 risc5x/hex_conv/jumptest.hex http://www.opencores.org/cvsweb.shtml/risc5x/hex_conv/jumptest.hex?rev=1.1&content-type=text/x-cvsweb-markup Index: jumptest.hex =================================================================== :10000000FF0C050040000600070026000B0C220034 :10001000F00C2600F30A050CE201F10C2600F30AAD :10002000170A0000040CA200F20C2600F30A100CC0 :100030002400FF0C2000A40284061A0A100C2900D8 :10004000200C2A00090C24000402890F4307F30A3C :100050000002100F4307F30A150C20000902150FC8 :100060004307F30AA4020002200F4307F30A000C1F :100070002400A50C0002000F4307F30A000C240023 :100080001F0C3F00200C24003F0C3F00400C2400BC :100090005F0C3F00600C24007F0C3F00000C24002C :1000A0001F021F0F4307F30A200C24001F023F0FFB :1000B0004307F30A400C24001F025F0F4307F30AB3 :1000C000600C24001F027F0F4307F30A000C24007A :1000D000450C2F00600C2400540C2F00400C240011 :1000E0000F02540F4306770AF30C2600F30A000CA4 :1000F0002400040C2900E900E900E900E900E90016 :100100000902FF0F4307F30AA902A9020902010F1E :100110004307F30A6900A50C2901A903F00C690142 :1001200069025A0CA9010902F50F43069A0AF40C58 :100130002600F30A230C2900E10CE9010307F30A66 :10014000020CA9000307F30A340CA9000306F30A02 :100150000902CE0F4307F30A340C29000F0CE90102 :100160000306F30A2307F30A010CA9000307F30AA5 :100170002307F30AFF0CA9000306F30A2306F30A78 :100180000902430F4307F30AE00C26000502290089 :10019000230C2A006B006C00090203040A06EB0121 :1001A0002B032C032A06EB012B032C034A06EB013D :1001B0002B032C036A06EB012B032C038A06EB01AD :1001C0002B032C03AA06EB012B032C03CA06EB011D :1001D0002B032C03EA06EB012B032C030C02260055 :0801E0000B022700C60AF30A16 :00000001FF 1.1 risc5x/hex_conv/jumptest.ucf http://www.opencores.org/cvsweb.shtml/risc5x/hex_conv/jumptest.ucf?rev=1.1&content-type=text/x-cvsweb-markup Index: jumptest.ucf =================================================================== INST PRAMS_0_INST INIT_00 = 55503BF30C0D0FF0FF0FF0FF0F0F0F0F0F043C0F51F0F418480C3A83E678BB87; INST PRAMS_0_INST INIT_01 = 000000EF83E3E3E3E3E3E3E3ED3B58FDFF7FF5FF74F9F4F6F57E2D59455F55FD; INST PRAMS_0_INST INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_0_INST INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_00 = AAA504474D4D40F40F40F40F4F4F4F4F4005001061000968894D041110442547; INST PRAMS_1_INST INIT_01 = 000000167EAEAEAEAEAEAEAEA2E8940200B00800B90E0908088161AA8A602A0E; INST PRAMS_1_INST INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_1_INST INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_00 = AAA23BC489A88CDAC58CDAC58FAD8FAD8C0A322C49C4C08A94AE7B81EE3B8803; INST PRAMS_2_INST INIT_01 = 000000C88AAA8AAA8AAA8AAA80AA8AC0ECBEC8EC8BC0CBC8CAAED326BAAC0ACC; INST PRAMS_2_INST INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_2_INST INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_00 = FFC0335411110D41D41D00D0011110000D08342D00D0D800028C3380CF330013; INST PRAMS_3_INST INIT_01 = 000000F000F0F0E0E0D0D0C0C05003D4CCBCC8CCC0DCC8C8CF0CE725789D0ADC; INST PRAMS_3_INST INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_3_INST INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_00 = 000020AE00000BE0BE0BE0BE000000000BE02FABE0BEBE000A80200281200000; INST PRAMS_4_INST INIT_01 = 000000A22F6F6F6F6F6F6F6F620020BEAA0BB0BA40BEA0B0B4082B924D0BEABE; INST PRAMS_4_INST INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_4_INST INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_00 = 000CE39C333339C39C39C39C3333333339CCE709C39C9C33390CE3328CE33003; INST PRAMS_5_INST INIT_01 = 000000A000101010101010101403039C99399399339C93939338E70C30C9C09C; INST PRAMS_5_INST INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000; INST PRAMS_5_INST INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000; 1.1 risc5x/hex_conv/readme.txt http://www.opencores.org/cvsweb.shtml/risc5x/hex_conv/readme.txt?rev=1.1&content-type=text/x-cvsweb-markup Index: readme.txt =================================================================== -- -- Risc5x -- www.OpenCores.Org - November 2001 -- -- -- This library is free software; you can distribute it and/or modify it -- under the terms of the GNU Lesser General Public License as published -- by the Free Software Foundation; either version 2.1 of the License, or -- (at your option) any later version. -- -- This library is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -- See the GNU Lesser General Public License for more details. -- -- A RISC CPU core. -- -- (c) Mike Johnson 2001. All Rights Reserved. -- mikej@o... for support or any other issues. -- -- Revision list -- -- version 1.1 bug fix: Used wrong bank select bits in direct addressing mode -- INDF register returns 0 when indirectly read -- FSR bit 8 always set -- (cpu.vhd file changed) -- -- version 1.0 initial opencores release -- Risc5x is a small RISC CPU written in VHDL that is compatible with the 12 bit opcode PIC family. Single cycle operation normally, two cycles when the program counter is modified. Clock speeds of over 40Mhz are possible when using the Xilinx Virtex optimisations. This program ( hexconv.cpp ) may be used to read in a .HEX program file and outputs directives to the Xilinx build tools to initialise the program ram correctly. Usage : hexconv sourcefile.hex outputs to screen hexconv sourcefile.hex > temp.ucf outputs to file temp.ucf this will generate 16 x 6 statements like this : INST PRAMS_0_INST INIT_00 = 00000000000000000000000000000000000000000000000000000000E9A7B9E4; copy these to your RISC5X_XIL.UCF file. Job done. The program source has a commented out section which will produce "attribute init" statements which may be used in the VHDL code directly. Replace the prams generate in RISC5X_XIL.vhd with the following. The advantage of this technique is you can see the correct init's in the EDIF file, and if you have a block ram simulation model that you can pass INIT generics to, then you can simulate it. prams : if true generate attribute INIT_00 of inst0 : label is "00000000000000000000000000000000000000000000000000000000E9A7B9E4"; <etc for all 16 x 6> begin inst0 : ramb4_s2_s2 port map ( dob => pdata(1 downto 0), dib => "00", <etc> doa => pram_dout(1 downto 0), dia => pram_din(1 downto 0), <etc> ); inst1 : ramb4_s2_s2 port map ( dob => pdata(3 downto 2), <etc> doa => pram_dout(3 downto 2), dia => pram_din(3 downto 2), <etc> ); <etc upto inst 5> end generate; Legal Stuff This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. You are responsible for any legal issues arising from the use of this core. The source files may be used and distributed without restriction provided that all copyright statements are not removed from the files and that any derivative work contains the original copyright notices and the associated disclaimer. PIC is a trademark of Microchip Technology Inc. Any questions or interest in customisation /locked / other cores (16x8x?) etc feel free to mail. mikej@o... Cheers Mike.

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.