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From: OpenCores CVS Agent<cvs@o...>
Date: Thu Jan 27 15:14:36 CET 2005
Subject: [cvs-checkins] MODIFIED: or1k ...

Date: 00/05/01 27:15:14

Modified: or1k/or1ksim/cpu/or32 execute.c or32.c generate.c Log: Remove the global op structure Revision Changes Path 1.101 +164 -119 or1k/or1ksim/cpu/or32/execute.c http://www.opencores.org/cvsweb.shtml/or1k/or1ksim/cpu/or32/execute.c.diff?r1=1.100&r2=1.101 (In the diff below, changes in quantity of whitespace are not shown.) Index: execute.c =================================================================== RCS file: /cvsroot/nogj/or1k/or1ksim/cpu/or32/execute.c,v retrieving revision 1.100 retrieving revision 1.101 diff -u -b -r1.100 -r1.101 --- execute.c 27 Jan 2005 13:51:22 -0000 1.100 +++ execute.c 27 Jan 2005 14:14:08 -0000 1.101 @@ -1,5 +1,6 @@ /* execute.c -- OR1K architecture dependent simulation Copyright (C) 1999 Damjan Lampret, lampret@o... + Copyright (C) 2005 György `nog' Jeney, nog@s... This file is part of OpenRISC 1000 Architectural Simulator. @@ -102,8 +103,10 @@ /* Local data needed for execution. */ static int next_delay_insn; static int breakpoint; -static unsigned long *op; -static int num_op; + +/* Effective address of instructions that have an effective address. This is + * only used to get dump_exe_log correct */ +static unsigned long insn_ea; /* Implementation specific. Get an actual value of a specific register. */ @@ -182,7 +185,34 @@ } } -/* Does srcoperand depend on computation of dstoperand? Return +/* Implementation specific. + Evaluates source operand opd. */ + +static unsigned long eval_operand_val(unsigned long insn, + struct insn_op_struct *opd) +{ + unsigned long operand = 0; + unsigned long sbit; + unsigned int nbits = 0; + + while(1) { + operand |= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits; + nbits += opd->data; + + if(opd->type & OPTYPE_OP) + break; + opd++; + } + + if(opd->type & OPTYPE_SIG) { + sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR; + if(operand & (1 << sbit)) operand |= 0xffffffff << sbit; + } + + return operand; +} + +/* Does source operand depend on computation of dstoperand? Return non-zero if yes. Cycle t Cycle t+1 @@ -201,40 +231,61 @@ { /* Find destination type. */ unsigned long type = 0; - int i = 0; + int prev_dis, next_dis; + unsigned int prev_reg_val = 0; + struct insn_op_struct *opd; + if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG && or32_opcodes[next->insn_index].flags & OR32_R_FLAG) return 1; - while (!(prev->op[i + MAX_OPERANDS] & OPTYPE_LAST)) - if (prev->op[i + MAX_OPERANDS] & OPTYPE_DST) - { - type = prev->op[i + MAX_OPERANDS]; + opd = op_start[prev->insn_index]; + prev_dis = 0; + + while (1) { + if (opd->type & OPTYPE_DIS) + prev_dis = 1; + + if (opd->type & OPTYPE_DST) { + type = opd->type; + if (prev_dis) + type |= OPTYPE_DIS; + /* Destination is always a register */ + prev_reg_val = eval_operand_val (prev->insn, opd); break; } - else - i++; + if (opd->type & OPTYPE_LAST) + return 0; /* Doesn't have a destination operand */ + if (opd->type & OPTYPE_OP) + prev_dis = 0; + opd++; + } /* We search all source operands - if we find confict => return 1 */ - i = 0; - while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST)) - if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST)) - { - if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS) { - if (type & OPTYPE_DIS) - return 1; - else if (next->op[i] == prev->op[i] - && (next->op[i + MAX_OPERANDS] & OPTYPE_REG)) + opd = op_start[next->insn_index]; + next_dis = 0; + + while (1) { + if (opd->type & OPTYPE_DIS) + next_dis = 1; + /* This instruction sequence also depends on order of execution: + * l.lw r1, k(r1) + * l.sw k(r1), r4 + * Here r1 is a destination in l.sw */ + /* FIXME: This situation is not handeld here when r1 == r2: + * l.sw k(r1), r4 + * l.lw r3, k(r2) + */ + if (!(opd->type & OPTYPE_DST) || (next_dis && (opd->type & OPTYPE_DST))) { + if (opd->type & OPTYPE_REG) + if (eval_operand_val (next->insn, opd) == prev_reg_val) return 1; } - if (next->op[i] == prev->op[i] - && (next->op[i + MAX_OPERANDS] & OPTYPE_REG) - && (type & OPTYPE_REG)) - return 1; - i++; + if (opd->type & OPTYPE_LAST) + break; + opd++; } - else - i++; + return 0; } @@ -427,18 +478,26 @@ /* Outputs dissasembled instruction */ void dump_exe_log () { - unsigned long i = iqueue[0].insn_addr; + unsigned long insn_addr = iqueue[0].insn_addr; + unsigned long i, j; - if (i == 0xffffffff) return; - if (config.sim.exe_log_start <= runtime.cpu.instructions && (config.sim.exe_log_end <= 0 || runtime.cpu.instructions <= config.sim.exe_log_end)) { - if (config.sim.exe_log_marker && runtime.cpu.instructions % config.sim.exe_log_marker == 0) { + if (insn_addr == 0xffffffff) return; + if ((config.sim.exe_log_start <= runtime.cpu.instructions) && + ((config.sim.exe_log_end <= 0) || + (runtime.cpu.instructions <= config.sim.exe_log_end))) { + if (config.sim.exe_log_marker && + !(runtime.cpu.instructions % config.sim.exe_log_marker)) { fprintf (runtime.sim.fexe_log, "--------------------- %8lli instruction ---------------------\n", runtime.cpu.instructions); } switch (config.sim.exe_log_type) { case EXE_LOG_HARDWARE: - fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11llu): %.8lx: ", runtime.cpu.instructions, i); - fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i), evalsim_mem8_void(i + 1)); - fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i + 2), evalsim_mem8_void(i + 3)); + fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11llu): %.8lx: ", + runtime.cpu.instructions, insn_addr); + fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(insn_addr), + evalsim_mem8_void(insn_addr + 1)); + fprintf (runtime.sim.fexe_log, "%.2x%.2x", + evalsim_mem8_void(insn_addr + 2), + evalsim_mem8_void(insn_addr + 3)); for(i = 0; i < MAX_GPRS; i++) { if (i % 4 == 0) fprintf(runtime.sim.fexe_log, "\n"); @@ -457,30 +516,40 @@ disassemble_index (iqueue[0].insn, iqueue[0].insn_index); { struct label_entry *entry; - entry = get_label(i); + entry = get_label(insn_addr); if (entry) fprintf (runtime.sim.fexe_log, "%s:\n", entry->name); } if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) { - int i,j=0; + struct insn_op_struct *opd = op_start[iqueue[0].insn_index]; - for (i = 0; i < num_op; i++) - if (op[i + MAX_OPERANDS] & OPTYPE_DIS) { - j=1; - fprintf (runtime.sim.fexe_log, "EA =%08lx PA =%08lx ", op[i], - peek_into_dtlb(op[i],0,0)); - } else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) { - fprintf (runtime.sim.fexe_log, "r%-2li=%08lx ", op[i], - evalsim_reg32 (op[i])); + j = 0; + while (1) { + i = eval_operand_val (iqueue[0].insn, opd); + while (!(opd->type & OPTYPE_OP)) + opd++; + if (opd->type & OPTYPE_DIS) { + fprintf (runtime.sim.fexe_log, "EA =%08lx PA =%08lx ", insn_ea, + peek_into_dtlb(insn_ea,0,0)); + opd++; /* Skip of register operand */ + j++; + } else if ((opd->type & OPTYPE_REG) && i) { + fprintf (runtime.sim.fexe_log, "r%-2li=%08lx ", i, + evalsim_reg32 (i)); } else fprintf (runtime.sim.fexe_log, " "); - - i+=j; - for (; i < 3; i++) + j++; + if(opd->type & OPTYPE_LAST) + break; + opd++; + } + while(j < 3) { fprintf (runtime.sim.fexe_log, " "); + j++; + } } - fprintf (runtime.sim.fexe_log, "%.8lx ", i); + fprintf (runtime.sim.fexe_log, "%.8lx ", insn_addr); fprintf (runtime.sim.fexe_log, "%s\n", disassembled); } } @@ -630,84 +699,62 @@ #define INSTRUCTION(name) void name (struct iqueue_entry *current) /* Implementation specific. - Parses and returns operands. */ + Evaluates source operand op_no. */ -static void -eval_operands (unsigned long insn, int insn_index, int* breakpoint) +static unsigned long eval_operand (int op_no, unsigned long insn_index, + unsigned long insn) { struct insn_op_struct *opd = op_start[insn_index]; - unsigned long data = 0; - int dis = 0; - int no = 0; + unsigned long ret; - while (1) - { - unsigned long tmp = 0, nbits = 0; - while (1) - { - tmp |= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits; - nbits += opd->data; - if (opd->type & OPTYPE_OP) - break; + while (op_no) { + if(opd->type & OPTYPE_LAST) { + fprintf (stderr, "Instruction requested more operands than it has\n"); + exit (1); + } + if((opd->type & OPTYPE_OP) && !(opd->type & OPTYPE_DIS)) + op_no--; opd++; } - /* Do we have to sign extend? */ - if (opd->type & OPTYPE_SIG) - { - int sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR; - if (tmp & (1 << sbit)) - tmp |= 0xFFFFFFFF << sbit; - } if (opd->type & OPTYPE_DIS) { - /* We have to read register later. */ - data += tmp; - dis = 1; - } else - { - if (dis && (opd->type & OPTYPE_REG)) - op[no] = data + eval_reg32 (tmp); - else - op[no] = tmp; - op[no + MAX_OPERANDS] = opd->type | (dis ? OPTYPE_DIS : 0); - no++; - data = 0; - dis = 0; - } - if(opd->type & OPTYPE_LAST) { - num_op = no; - return; - } + ret = eval_operand_val (insn, opd); + while (!(opd->type & OPTYPE_OP)) + opd++; opd++; + ret += eval_reg32 (eval_operand_val (insn, opd)); + insn_ea = ret; + return ret; } - num_op = no; -} + if (opd->type & OPTYPE_REG) + return eval_reg32 (eval_operand_val (insn, opd)); -/* Implementation specific. - Evaluates source operand op_no. */ - -static unsigned long eval_operand (int op_no) -{ - if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) { - return op[op_no]; - } else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) { - return eval_reg32 (op[op_no]); - } else { - return op[op_no]; - } + return eval_operand_val (insn, opd); } /* Implementation specific. Set destination operand (reister direct) with value. */ -inline static void set_operand(int op_no, unsigned long value) +inline static void set_operand(int op_no, unsigned long value, + unsigned long insn_index, unsigned long insn) { - /* Mark this as destination operand. */ - if (!(op[op_no + MAX_OPERANDS] & OPTYPE_REG)) { + struct insn_op_struct *opd = op_start[insn_index]; + + while (op_no) { + if(opd->type & OPTYPE_LAST) { + fprintf (stderr, "Instruction requested more operands than it has\n"); + exit (1); + } + if((opd->type & OPTYPE_OP) && !(opd->type & OPTYPE_DIS)) + op_no--; + opd++; + } + + if (!(opd->type & OPTYPE_REG)) { fprintf (stderr, "Trying to set a non-register operand\n"); exit (1); } - set_reg32(op[op_no], value); + set_reg32 (eval_operand_val (insn, opd), value); } /* Simple and rather slow decoding function based on built automata. */ @@ -720,18 +767,16 @@ if (insn_index < 0) l_invalid(current); else { - op = &current->op[0]; - eval_operands (current->insn, insn_index, &breakpoint); or32_opcodes[insn_index].exec(current); } if (do_stats) analysis(&iqueue[0]); } -#define SET_PARAM0(val) set_operand(0, val) +#define SET_PARAM0(val) set_operand(0, val, current->insn_index, current->insn) -#define PARAM0 eval_operand(0) -#define PARAM1 eval_operand(1) -#define PARAM2 eval_operand(2) +#define PARAM0 eval_operand(0, current->insn_index, current->insn) +#define PARAM1 eval_operand(1, current->insn_index, current->insn) +#define PARAM2 eval_operand(2, current->insn_index, current->insn) #include "insnset.c" 1.40 +480 -247 or1k/or1ksim/cpu/or32/or32.c http://www.opencores.org/cvsweb.shtml/or1k/or1ksim/cpu/or32/or32.c.diff?r1=1.39&r2=1.40 (In the diff below, changes in quantity of whitespace are not shown.) Index: or32.c =================================================================== RCS file: /cvsroot/nogj/or1k/or1ksim/cpu/or32/or32.c,v retrieving revision 1.39 retrieving revision 1.40 diff -u -b -r1.39 -r1.40 --- or32.c 27 Jan 2005 13:35:40 -0000 1.39 +++ or32.c 27 Jan 2005 14:14:13 -0000 1.40 @@ -20,6 +20,9 @@ /* * $Log: or32.c,v $ + * Revision 1.40 2005/01/27 14:14:13 nogj + * Remove the global op structure + * * Revision 1.39 2005/01/27 13:35:40 nogj * * Fix generate.c to produce a execgen.c with less warnings. * * Fix the --enable-simple configure option. @@ -118,256 +121,478 @@ CONST struct or32_opcode or32_opcodes[] = { -{ "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY }, -{ "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY }, -{ "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG}, -{ "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG }, -{ "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 }, -{ "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/ -{ "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/ - -{ "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 }, -{ "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */ -{ "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 }, -{ "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 }, -{ "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 }, -{ "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY }, - -{ "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, -{ "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, -{ "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, -{ "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, -{ "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, -{ "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, -{ "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, -{ "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, -{ "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, -{ "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, -{ "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, -{ "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, -{ "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 }, -{ "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 }, -{ "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 }, -{ "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 }, -{ "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 }, -{ "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 }, -{ "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 }, -{ "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 }, -{ "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 }, -{ "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 }, -{ "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 }, -{ "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 }, -{ "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 }, -{ "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 }, -{ "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 }, -{ "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 }, -{ "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 }, -{ "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 }, -{ "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 }, -{ "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 }, -{ "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 }, -{ "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 }, -{ "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 }, -{ "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 }, -{ "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 }, -{ "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 }, -{ "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 }, -{ "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 }, -{ "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 }, -{ "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 }, -{ "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 }, -{ "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 }, -{ "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 }, -{ "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 }, -{ "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 }, -{ "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 }, -{ "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 }, -{ "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 }, -{ "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 }, -{ "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 }, -{ "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 }, -{ "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 }, -{ "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 }, -{ "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 }, -{ "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 }, -{ "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 }, -{ "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 }, -{ "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 }, -{ "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 }, -{ "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 }, -{ "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 }, -{ "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 }, -{ "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 }, -{ "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 }, -{ "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 }, -{ "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 }, -{ "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 }, -{ "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 }, -{ "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 }, -{ "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 }, -{ "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 }, -{ "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 }, -{ "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 }, -{ "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 }, -{ "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 }, -{ "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 }, -{ "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 }, -{ "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 }, -{ "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 }, -{ "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 }, -{ "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 }, -{ "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 }, -{ "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 }, -{ "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 }, -{ "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 }, -{ "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 }, -{ "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 }, -{ "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 }, -{ "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 }, - -{ "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY }, -{ "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY }, -{ "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 }, -{ "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 }, -{ "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 }, -{ "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 }, -{ "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 }, - -{ "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, -{ "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 }, -{ "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, -{ "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 }, -{ "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 }, -{ "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 }, -{ "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 }, - -{ "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), OR32_W_FLAG }, -{ "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, -{ "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), OR32_W_FLAG }, -{ "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 }, -{ "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 }, -{ "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EF(l_mul), 0 }, -{ "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 }, -{ "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 }, -{ "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 }, -{ "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 }, -{ "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 }, - -{ "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG }, -{ "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG }, -{ "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG }, -{ "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG }, -{ "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG }, -{ "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG }, -{ "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG }, -{ "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG }, -{ "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG }, -{ "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG }, - -{ "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 }, -{ "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/ -{ "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/ - -{ "lf.add.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x0", EF(lf_add_s), 0 }, -{ "lf.sub.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x1", EF(lf_sub_s), 0 }, -{ "lf.mul.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x2", EF(lf_mul_s), 0 }, -{ "lf.div.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x3", EF(lf_div_s), 0 }, -{ "lf.itof.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x4", EF(lf_itof_s), 0 }, -{ "lf.ftoi.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x5", EF(lf_ftoi_s), 0 }, -{ "lf.rem.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x6", EF(lf_rem_s), 0 }, -{ "lf.madd.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x7", EF(lf_madd_s), 0 }, -{ "lf.sfeq.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x8", EF(lf_sfeq_s), 0 }, -{ "lf.sfne.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x9", EF(lf_sfne_s), 0 }, -{ "lf.sfgt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xA", EF(lf_sfgt_s), 0 }, -{ "lf.sfge.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xB", EF(lf_sfge_s), 0 }, -{ "lf.sflt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xC", EF(lf_sflt_s), 0 }, -{ "lf.sfle.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xD", EF(lf_sfle_s), 0 }, -{ "lf.cust1.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xD ----", EFI, 0 }, - -{ "lf.add.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, -{ "lf.sub.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, -{ "lf.mul.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, -{ "lf.div.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, -{ "lf.itof.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x4", EFI, 0 }, -{ "lf.ftoi.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x5", EFI, 0 }, -{ "lf.rem.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, -{ "lf.madd.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, -{ "lf.sfeq.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, -{ "lf.sfne.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, -{ "lf.sfgt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, -{ "lf.sfge.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, -{ "lf.sflt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, -{ "lf.sfle.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, -{ "lf.cust1.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xE ----", EFI, 0 }, - -{ "l.sd", "I(rD),rB", "11 0x4 IIIII DDDDD BBBB BIII IIII IIII", EFI, 0 }, -{ "l.sw", "I(rD),rB", "11 0x5 IIIII DDDDD BBBB BIII IIII IIII", EF(l_sw), 0 }, -{ "l.sb", "I(rD),rB", "11 0x6 IIIII DDDDD BBBB BIII IIII IIII", EF(l_sb), 0 }, -{ "l.sh", "I(rD),rB", "11 0x7 IIIII DDDDD BBBB BIII IIII IIII", EF(l_sh), 0 }, - -{ "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), OR32_W_FLAG }, -{ "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EF(l_addc), OR32_W_FLAG }, -{ "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 }, -{ "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), OR32_W_FLAG }, -{ "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 }, -{ "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 }, -{ "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 }, - -{ "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 }, -{ "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 }, -{ "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 }, -{ "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 }, -{ "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x9", EF(l_div), 0 }, -{ "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xA", EF(l_divu), 0 }, -{ "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 }, -{ "l.extbs", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xC", EF(l_extbs), 0 }, -{ "l.exths", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xC", EF(l_exths), 0 }, -{ "l.extws", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xD", EF(l_extws), 0 }, -{ "l.extbz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 11-- 0xC", EF(l_extbz), 0 }, -{ "l.exthz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 10-- 0xC", EF(l_exthz), 0 }, -{ "l.extwz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xD", EF(l_extwz), 0 }, -{ "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EF(l_cmov), OR32_R_FLAG }, -{ "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EF(l_ff1), 0 }, - -{ "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG }, -{ "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG }, -{ "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG }, -{ "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG }, -{ "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG }, -{ "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG }, -{ "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG }, -{ "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG }, -{ "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG }, -{ "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG }, - -{ "l.cust5", "rD,rA,rB,L,K", "11 0xC DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI, 0 }, -{ "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 }, -{ "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 }, -{ "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 }, +{ "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", + EF(l_j), OR32_IF_DELAY, it_jump }, +{ "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", + EF(l_jal), OR32_IF_DELAY, it_jump }, +{ "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", + EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG, it_branch }, +{ "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", + EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG, it_branch }, +{ "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", + EF(l_nop), 0, it_nop }, +{ "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", + EF(l_movhi), 0, it_movimm }, +{ "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", + EF(l_macrc), 0, it_mac }, +{ "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", + EF(l_sys), 0, it_unknown }, +{ "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", + EF(l_trap), 0, it_unknown }, +{ "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, + 0, it_unknown }, +{ "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, + 0, it_unknown }, +{ "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, + 0, it_unknown }, +{ "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", + EF(l_rfe), OR32_IF_DELAY, it_exception }, +{ "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0, + it_unknown }, +{ "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0, + it_unknown }, +{ "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0, + it_unknown }, +{ "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0, + it_unknown }, +{ "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0, + it_unknown }, +{ "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0, + it_unknown }, +{ "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0, + it_unknown }, +{ "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0, + it_unknown }, +{ "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0, + it_unknown }, +{ "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0, + it_unknown }, +{ "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0, + it_unknown }, +{ "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0, + it_unknown }, +{ "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0, + it_unknown }, +{ "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0, + it_unknown }, +{ "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0, + it_unknown }, +{ "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0, + it_unknown }, +{ "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0, + it_unknown }, +{ "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0, + it_unknown }, +{ "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0, + it_unknown }, +{ "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0, + it_unknown }, +{ "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0, + it_unknown }, +{ "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0, + it_unknown }, +{ "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0, + it_unknown }, +{ "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0, + it_unknown }, +{ "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0, + it_unknown }, +{ "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0, + it_unknown }, +{ "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0, + it_unknown }, +{ "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0, + it_unknown }, +{ "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0, + it_unknown }, +{ "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0, + it_unknown }, +{ "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0, + it_unknown }, +{ "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0, + it_unknown }, +{ "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0, + it_unknown }, +{ "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0, + it_unknown }, +{ "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0, + it_unknown }, +{ "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0, + it_unknown }, +{ "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0, + it_unknown }, +{ "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0, + it_unknown }, +{ "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0, + it_unknown }, +{ "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0, + it_unknown }, +{ "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0, + it_unknown }, +{ "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0, + it_unknown }, +{ "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0, + it_unknown }, +{ "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0, + it_unknown }, +{ "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0, + it_unknown }, +{ "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0, + it_unknown }, +{ "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0, + it_unknown }, +{ "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0, + it_unknown }, +{ "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0, + it_unknown }, +{ "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0, + it_unknown }, +{ "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0, + it_unknown }, +{ "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0, + it_unknown }, +{ "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0, + it_unknown }, +{ "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0, + it_unknown }, +{ "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0, + it_unknown }, +{ "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0, + it_unknown }, +{ "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0, + it_unknown }, +{ "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0, + it_unknown }, +{ "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0, + it_unknown }, +{ "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0, + it_unknown }, +{ "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0, + it_unknown }, +{ "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0, + it_unknown }, +{ "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0, + it_unknown }, +{ "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0, + it_unknown }, +{ "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0, + it_unknown }, +{ "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0, + it_unknown }, +{ "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0, + it_unknown }, +{ "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0, + it_unknown }, +{ "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0, + it_unknown }, +{ "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0, + it_unknown }, +{ "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0, + it_unknown }, +{ "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0, + it_unknown }, +{ "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0, + it_unknown }, +{ "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0, + it_unknown }, +{ "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0, + it_unknown }, +{ "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0, + it_unknown }, +{ "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0, + it_unknown }, +{ "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0, + it_unknown }, +{ "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0, + it_unknown }, +{ "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0, + it_unknown }, +{ "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0, + it_unknown }, +{ "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0, + it_unknown }, +{ "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0, + it_unknown }, +{ "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0, + it_unknown }, +{ "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0, + it_unknown }, +{ "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0, + it_unknown }, +{ "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0, + it_unknown }, +{ "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0, + it_unknown }, +{ "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0, + it_unknown }, +{ "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0, + it_unknown }, +{ "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0, + it_unknown }, + +{ "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", + EF(l_jr), OR32_IF_DELAY, it_jump }, +{ "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", + EF(l_jalr), OR32_IF_DELAY, it_jump }, +{ "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", + EF(l_mac), 0, it_mac }, +{ "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", + EF(l_cust1), 0, it_unknown }, +{ "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", + EF(l_cust2), 0, it_unknown }, +{ "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", + EF(l_cust3), 0, it_unknown }, +{ "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", + EF(l_cust4), 0, it_unknown }, + +{ "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, + 0, it_load }, +{ "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", + EF(l_lwz), 0, it_load }, +{ "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, + 0, it_load }, +{ "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", + EF(l_lbz), 0, it_load }, +{ "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", + EF(l_lbs), 0, it_load }, +{ "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", + EF(l_lhz), 0, it_load }, +{ "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", + EF(l_lhs), 0, it_load }, + +{ "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", + EF(l_add), OR32_W_FLAG, it_arith }, +{ "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, + 0, it_arith }, +{ "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", + EF(l_and), OR32_W_FLAG, it_arith }, +{ "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", + EF(l_or), 0, it_arith }, +{ "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", + EF(l_xor), 0, it_arith }, +{ "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", + EF(l_mul), 0, it_arith }, +{ "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", + EF(l_mfspr), 0, it_move }, +{ "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", + EF(l_sll), 0, it_shift }, +{ "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", + EF(l_srl), 0, it_shift }, +{ "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", + EF(l_sra), 0, it_shift }, +{ "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, + 0, it_shift }, + +{ "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", + EF(l_sfeq), OR32_W_FLAG, it_compare }, +{ "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", + EF(l_sfne), OR32_W_FLAG, it_compare }, +{ "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", + EF(l_sfgtu), OR32_W_FLAG, it_compare }, +{ "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", + EF(l_sfgeu), OR32_W_FLAG, it_compare }, +{ "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", + EF(l_sfltu), OR32_W_FLAG, it_compare }, +{ "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", + EF(l_sfleu), OR32_W_FLAG, it_compare }, +{ "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", + EF(l_sfgts), OR32_W_FLAG, it_compare }, +{ "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", + EF(l_sfges), OR32_W_FLAG, it_compare }, +{ "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", + EF(l_sflts), OR32_W_FLAG, it_compare }, +{ "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", + EF(l_sfles), OR32_W_FLAG, it_compare }, + +{ "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", + EF(l_mtspr), 0, it_move }, +{ "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", + EF(l_mac), 0, it_mac }, +{ "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", + EF(l_msb), 0, it_mac }, + +{ "lf.add.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x0", + EF(lf_add_s), 0, it_float }, +{ "lf.sub.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x1", + EF(lf_sub_s), 0, it_float }, +{ "lf.mul.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x2", + EF(lf_mul_s), 0, it_float }, +{ "lf.div.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x3", + EF(lf_div_s), 0, it_float }, +{ "lf.itof.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x4", + EF(lf_itof_s), 0, it_float }, +{ "lf.ftoi.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x5", + EF(lf_ftoi_s), 0, it_float }, +{ "lf.rem.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x6", + EF(lf_rem_s), 0, it_float }, +{ "lf.madd.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x7", + EF(lf_madd_s), 0, it_float }, +{ "lf.sfeq.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x8", + EF(lf_sfeq_s), 0, it_float }, +{ "lf.sfne.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x9", + EF(lf_sfne_s), 0, it_float }, +{ "lf.sfgt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xA", + EF(lf_sfgt_s), 0, it_float }, +{ "lf.sfge.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xB", + EF(lf_sfge_s), 0, it_float }, +{ "lf.sflt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xC", + EF(lf_sflt_s), 0, it_float }, +{ "lf.sfle.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xD", + EF(lf_sfle_s), 0, it_float }, +{ "lf.cust1.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xD ----", EFI, + 0, it_float }, + +{ "lf.add.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0, + it_float }, +{ "lf.sub.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0, + it_float }, +{ "lf.mul.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0, + it_float }, +{ "lf.div.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0, + it_float }, +{ "lf.itof.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x4", EFI, 0, + it_float }, +{ "lf.ftoi.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x5", EFI, 0, + it_float }, +{ "lf.rem.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0, + it_float }, +{ "lf.madd.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0, + it_float }, +{ "lf.sfeq.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0, + it_float }, +{ "lf.sfne.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0, + it_float }, +{ "lf.sfgt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0, + it_float }, +{ "lf.sfge.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0, + it_float }, +{ "lf.sflt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0, + it_float }, +{ "lf.sfle.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0, + it_float }, +{ "lf.cust1.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xE ----", EFI, 0, + it_float }, + +{ "l.sd", "I(rD),rB", "11 0x4 IIIII DDDDD BBBB BIII IIII IIII", EFI, + 0, it_store }, +{ "l.sw", "I(rD),rB", "11 0x5 IIIII DDDDD BBBB BIII IIII IIII", + EF(l_sw), 0, it_store }, +{ "l.sb", "I(rD),rB", "11 0x6 IIIII DDDDD BBBB BIII IIII IIII", + EF(l_sb), 0, it_store }, +{ "l.sh", "I(rD),rB", "11 0x7 IIIII DDDDD BBBB BIII IIII IIII", + EF(l_sh), 0, it_store }, + +{ "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", + EF(l_add), OR32_W_FLAG, it_arith }, +{ "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", + EF(l_addc), OR32_W_FLAG, it_arith }, +{ "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", + EF(l_sub), 0, it_arith }, +{ "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", + EF(l_and), OR32_W_FLAG, it_arith }, +{ "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", + EF(l_or), 0, it_arith }, +{ "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", + EF(l_xor), 0, it_arith }, +{ "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", + EF(l_mul), 0, it_arith }, + +{ "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", + EF(l_sll), 0, it_shift }, +{ "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", + EF(l_srl), 0, it_shift }, +{ "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", + EF(l_sra), 0, it_shift }, +{ "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, + 0, it_shift }, +{ "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x9", + EF(l_div), 0, it_arith }, +{ "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xA", + EF(l_divu), 0, it_arith }, +{ "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, + 0, it_arith }, +{ "l.extbs", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xC", + EF(l_extbs), 0, it_move }, +{ "l.exths", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xC", + EF(l_exths), 0, it_move }, +{ "l.extws", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xD", + EF(l_extws), 0, it_move }, +{ "l.extbz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 11-- 0xC", + EF(l_extbz), 0, it_move }, +{ "l.exthz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 10-- 0xC", + EF(l_exthz), 0, it_move }, +{ "l.extwz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xD", + EF(l_extwz), 0, it_move }, +{ "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", + EF(l_cmov), OR32_R_FLAG, it_move }, +{ "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, + 0, it_arith }, + +{ "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", + EF(l_sfeq), OR32_W_FLAG, it_compare }, +{ "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", + EF(l_sfne), OR32_W_FLAG, it_compare }, +{ "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", + EF(l_sfgtu), OR32_W_FLAG, it_compare }, +{ "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", + EF(l_sfgeu), OR32_W_FLAG, it_compare }, +{ "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", + EF(l_sfltu), OR32_W_FLAG, it_compare }, +{ "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", + EF(l_sfleu), OR32_W_FLAG, it_compare }, +{ "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", + EF(l_sfgts), OR32_W_FLAG, it_compare }, +{ "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", + EF(l_sfges), OR32_W_FLAG, it_compare }, +{ "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", + EF(l_sflts), OR32_W_FLAG, it_compare }, +{ "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", + EF(l_sfles), OR32_W_FLAG, it_compare }, + +{ "l.cust5", "rD,rA,rB,L,K", "11 0xC DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI, + 0, it_unknown }, +{ "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, + 0, it_unknown }, /* This section should not be defined in or1ksim, since it contains duplicates, which would cause machine builder to complain. */ #ifdef HAS_CUST -{ "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 }, -{ "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, -{ "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, - -{ "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 }, -{ "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, -{ "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, - -{ "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 }, -{ "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, -{ "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, - -{ "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 }, -{ "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, -{ "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, +{ "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, + 0, it_unknown }, + +{ "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, + 0, it_unknown }, + +{ "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, + 0, it_unknown }, + +{ "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, + 0, it_unknown }, +{ "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, + 0, it_unknown }, #endif -{ "", "", "", EFI, 0 } /* Dummy entry, not included in num_opcodes. This - lets code examine entry i+1 without checking - if we've run off the end of the table. */ +{ "", "", "", EFI, 0, 0 } /* Dummy entry, not included in num_opcodes. This + * lets code examine entry i+1 without checking + * if we've run off the end of the table. */ }; #undef EFI @@ -645,6 +870,7 @@ { char *args = opcode->args; int i, type; + int num_cur_op = 0;; i = 0; type = 0; @@ -677,6 +903,7 @@ type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT; } + num_cur_op = 0; /* Split argument to sequences of consecutive ones. */ while (arg) { @@ -697,16 +924,21 @@ arg &= ~(((1 << mask) - 1) << shr); debug(6, "|%08X %08X\n", cur->type, cur->data); cur++; + num_cur_op++; } args++; } else if (*args == '(') { /* Next param is displacement. Later we will treat them as one operand. */ - cur--; - cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP; + /* Set the OPTYPE_DIS flag on all insn_op_structs that belong to this + * operand */ + while(num_cur_op > 0) { + cur[-num_cur_op].type |= type | OPTYPE_DIS; + num_cur_op--; + } + cur[-1].type |= OPTYPE_OP; debug(9, ">%08X %08X\n", cur->type, cur->data); - cur++; type = 0; i++; args++; 1.11 +10 -20 or1k/or1ksim/cpu/or32/generate.c http://www.opencores.org/cvsweb.shtml/or1k/or1ksim/cpu/or32/generate.c.diff?r1=1.10&r2=1.11 (In the diff below, changes in quantity of whitespace are not shown.) Index: generate.c =================================================================== RCS file: /cvsroot/nogj/or1k/or1ksim/cpu/or32/generate.c,v retrieving revision 1.10 retrieving revision 1.11 diff -u -b -r1.10 -r1.11 --- generate.c 27 Jan 2005 13:35:36 -0000 1.10 +++ generate.c 27 Jan 2005 14:14:14 -0000 1.11 @@ -30,7 +30,6 @@ static char *in_file; static char *out_file; -static unsigned long op[MAX_OPERANDS]; /* Whether this instruction stores something in register */ static int write_to_reg; @@ -129,8 +128,7 @@ return 0; } -/* Parses and puts operands into op[] structure. - Replacement for eval_operands routine. */ +/* Parses operands. */ static int gen_eval_operands (FILE *fo, int insn_index, int level) @@ -142,6 +140,7 @@ int set_param = 0; int dis = 0; int sbit; + int dis_op = -1; write_to_reg = 0; @@ -188,7 +187,7 @@ nbits += opd->data; - if (opd->type & OPTYPE_DIS) { + if ((opd->type & OPTYPE_DIS) && (opd->type & OPTYPE_OP)) { sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR; if (opd->type & OPTYPE_SIG) shift_fprintf (level, fo, "if(%c & 0x%08x) %c |= 0x%x;\n", @@ -199,6 +198,7 @@ 'a' + num_ops, opd->type & OPTYPE_SHR, (1 << opd->data) - 1); dis = 1; + dis_op = num_ops; } if (opd->type & OPTYPE_OP) { @@ -220,10 +220,6 @@ shift_fprintf (level, fo, "#define PARAM%i %c\n", num_ops, 'a' + num_ops); } - - op[num_ops] = opd->type; - if(dis) - op[num_ops] |= OPTYPE_DIS; num_ops++; nbits = 0; dis = 0; @@ -243,39 +239,33 @@ for (i = 0; i < num_ops; i++) shift_fprintf (level, fo, "#undef PARAM%i\n", i); - return num_ops; + return dis_op; } /* Generates decode and execute for one instruction instance */ static int output_call (FILE *fo, int index, int level) { - int i; - int num_op; + int dis_op = -1; /*printf ("%i:%s\n", index, insn_name (index));*/ shift_fprintf (level++, fo, "{\n"); if (index >= 0) - num_op = gen_eval_operands (fo, index, level); - else - num_op = 0; + dis_op = gen_eval_operands (fo, index, level); if (index < 0) output_function (fo, "l_invalid", level); fprintf (fo, "\n"); shift_fprintf (level++, fo, "if (do_stats) {\n"); - shift_fprintf (level, fo, "num_op = %i;\n", num_op); - if (num_op) shift_fprintf (level, fo, "op = &current->op[0];\n"); + if (dis_op >= 0) + shift_fprintf (level, fo, "insn_ea = %c;\n", 'a' + dis_op); + shift_fprintf (level, fo, "current->insn_index = %i; /* \"%s\" */\n", index, insn_name (index)); - for (i = 0; i < num_op; i++) { - shift_fprintf (level, fo, "op[%i] = %c;\n", i, 'a' + i); - shift_fprintf (level, fo, "op[%i + MAX_OPERANDS] = 0x%08x;\n", i, op[i]); - } shift_fprintf (level, fo, "analysis(current);\n"); shift_fprintf (--level, fo, "}\n"); if (write_to_reg)