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Message
From: OpenCores CVS Agent<cvs@o...>
Date: Thu Jan 27 14:41:10 CET 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/01 27:14:41 Modified: or1k/or1ksim/cpu/or32 execute.c insnset.c
Log:
* Fix warnings in insnset.c and execute.c
Revision Changes Path
1.99 +4 -5 or1k/or1ksim/cpu/or32/execute.c
http://www.opencores.org/cvsweb.shtml/or1k/or1ksim/cpu/or32/execute.c.diff?r1=1.98&r2=1.99
(In the diff below, changes in quantity of whitespace are not shown.)
Index: execute.c
===================================================================
RCS file: /cvsroot/nogj/or1k/or1ksim/cpu/or32/execute.c,v
retrieving revision 1.98
retrieving revision 1.99
diff -u -b -r1.98 -r1.99
--- execute.c 27 Jan 2005 13:35:42 -0000 1.98
+++ execute.c 27 Jan 2005 13:41:05 -0000 1.99
@@ -242,9 +242,9 @@
/* Sets a new SPR_SR_OV value, based on next register value */
#if SET_OV_FLAG
-#define set_ov_flag(value) (((value) & 0x80000000 ? setsprbits (SPR_SR, SPR_SR_OV, 1) : setsprbits (SPR_SR, SPR_SR_OV, 0)), value)
+#define set_ov_flag(value) if((value) & 0x80000000) setsprbits (SPR_SR, SPR_SR_OV, 1); else setsprbits (SPR_SR, SPR_SR_OV, 0)
#else
-#define set_ov_flag(value) (value)
+#define set_ov_flag(value)
#endif
/* Modified by CZ 26/05/01 for new mode execution */
@@ -431,11 +431,11 @@
if (i == 0xffffffff) return;
if (config.sim.exe_log_start <= runtime.cpu.instructions && (config.sim.exe_log_end <= 0 || runtime.cpu.instructions <= config.sim.exe_log_end)) {
if (config.sim.exe_log_marker && runtime.cpu.instructions % config.sim.exe_log_marker == 0) {
- fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", runtime.cpu.instructions);
+ fprintf (runtime.sim.fexe_log, "--------------------- %8lli instruction ---------------------\n", runtime.cpu.instructions);
}
switch (config.sim.exe_log_type) {
case EXE_LOG_HARDWARE:
- fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11u): %.8lx: ", runtime.cpu.instructions, i);
+ fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11llu): %.8lx: ", runtime.cpu.instructions, i);
fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i), evalsim_mem8_void(i + 1));
fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i + 2), evalsim_mem8_void(i + 3));
for(i = 0; i < MAX_GPRS; i++) {
@@ -490,7 +490,6 @@
void dumpreg()
{
int i;
- char temp[100];
unsigned long physical_pc;
if ((physical_pc = peek_into_itlb(iqueue[0].insn_addr))) {
1.16 +17 -13 or1k/or1ksim/cpu/or32/insnset.c
http://www.opencores.org/cvsweb.shtml/or1k/or1ksim/cpu/or32/insnset.c.diff?r1=1.15&r2=1.16
(In the diff below, changes in quantity of whitespace are not shown.)
Index: insnset.c
===================================================================
RCS file: /cvsroot/nogj/or1k/or1ksim/cpu/or32/insnset.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -b -r1.15 -r1.16
--- insnset.c 27 Jan 2005 13:35:44 -0000 1.15
+++ insnset.c 27 Jan 2005 13:41:07 -0000 1.16
@@ -291,12 +291,13 @@
set_reg32(LINK_REGNO, pc + 8);
next_delay_insn = 1;
if (config.sim.profile) {
- struct mem_entry *entry;
struct label_entry *tmp;
if (verify_memoryarea(pcdelay) && (tmp = get_label (pcdelay)))
- fprintf (runtime.sim.fprof, "+%08X %08lX %08X %s\n", runtime.sim.cycles, pc + 8, pcdelay, tmp->name);
+ fprintf (runtime.sim.fprof, "+%08llX %08lX %08lX %s\n",
+ runtime.sim.cycles, pc + 8, pcdelay, tmp->name);
else
- fprintf (runtime.sim.fprof, "+%08X %08X %08X @%08X\n", runtime.sim.cycles, pc + 8, pcdelay, pcdelay);
+ fprintf (runtime.sim.fprof, "+%08llX %08lX %08lX @%08lX\n",
+ runtime.sim.cycles, pc + 8, pcdelay, pcdelay);
}
}
INSTRUCTION (l_jalr) {
@@ -310,7 +311,7 @@
pcdelay = PARAM0;
next_delay_insn = 1;
if (config.sim.profile)
- fprintf (runtime.sim.fprof, "-%08X %08X\n", runtime.sim.cycles, pcdelay);
+ fprintf (runtime.sim.fprof, "-%08llX %08lX\n", runtime.sim.cycles, pcdelay);
}
INSTRUCTION (l_rfe) {
IFF (config.cpu.dependstats) current->func_unit = it_exception;
@@ -325,11 +326,14 @@
case NOP_NOP:
break;
case NOP_EXIT:
- PRINTF("exit(%d)\n", evalsim_reg32 (3));
- fprintf(stderr, "@reset : cycles %lld, insn #%lld\n", runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
- fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
- fprintf(stderr, " diff : cycles %lld, insn #%lld\n", runtime.sim.cycles,
- runtime.sim.reset_cycles, runtime.cpu.instructions - runtime.cpu.reset_instructions);
+ PRINTF("exit(%ld)\n", evalsim_reg32 (3));
+ fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
+ runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
+ fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles,
+ runtime.cpu.instructions);
+ fprintf(stderr, " diff : cycles %lld, insn #%lld\n",
+ runtime.sim.cycles - runtime.sim.reset_cycles,
+ runtime.cpu.instructions - runtime.cpu.reset_instructions);
if (config.debug.gdb_enabled)
set_stall_state (1);
else
@@ -348,10 +352,10 @@
debug(5, "simprintf %x\n", stackaddr);
break;
case NOP_REPORT:
- PRINTF("report(0x%x);\n", evalsim_reg32(3));
+ PRINTF("report(0x%lx);\n", evalsim_reg32(3));
default:
if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
- PRINTF("report %i (0x%x);\n", k - NOP_REPORT_FIRST, evalsim_reg32(3));
+ PRINTF("report %i (0x%lx);\n", k - NOP_REPORT_FIRST, evalsim_reg32(3));
break;
}
}
@@ -490,7 +494,7 @@
hi = mfspr (SPR_MACHI);
x = PARAM0;
y = PARAM1;
- PRINTF ("[%08x,%08x]\t", (unsigned long)(x), (unsigned long)(y));
+ PRINTF ("[%08lx,%08lx]\t", (unsigned long)(x), (unsigned long)(y));
l = (ULONGEST)lo | ((LONGEST)hi << 32);
l += (LONGEST) x * (LONGEST) y;
@@ -510,7 +514,7 @@
hi = mfspr (SPR_MACHI);
x = PARAM0;
y = PARAM1;
- PRINTF ("[%08x,%08x]\t", (unsigned long)(x), (unsigned long)(y));
+ PRINTF ("[%08lx,%08lx]\t", (unsigned long)(x), (unsigned long)(y));
l = (ULONGEST)lo | ((LONGEST)hi << 32);
l -= x * y;
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