|
Message
From: OpenCores CVS Agent<cvs@o...>
Date: Thu Jan 27 14:36:55 CET 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/01 27:14:36 Modified: or1k/or1ksim/cpu/or32 generate.c or32.c execute.c insnset.c
Log:
* Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.
Revision Changes Path
1.10 +222 -212 or1k/or1ksim/cpu/or32/generate.c
http://www.opencores.org/cvsweb.shtml/or1k/or1ksim/cpu/or32/generate.c.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: generate.c
===================================================================
RCS file: /cvsroot/nogj/or1k/or1ksim/cpu/or32/generate.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- generate.c 19 Jul 2004 23:07:37 -0000 1.9
+++ generate.c 27 Jan 2005 13:35:36 -0000 1.10
@@ -1,5 +1,6 @@
/* generate.c -- generates file execgen.c from instruction set
Copyright (C) 1999 Damjan Lampret, lampret@o...
+ Copyright (C) 2005 György `nog' Jeney, nog@s...
This file is part of OpenRISC 1000 Architectural Simulator.
@@ -26,25 +27,17 @@
#include "config.h"
#include "opcode/or32.h"
#include "abstract.h"
-#include "labels.h"
-#include "parse.h"
-#include "execute.h"
-
-#define LEAF_FLAG (0x80000000)
-#define SHIFT {int i; for (i = 0; i < level; i++) fprintf (fo, " ");}
-
-extern unsigned long *automata;
-extern struct temp_insn_struct {
- unsigned long insn;
- unsigned long insn_mask;
- int in_pass;
-} *ti;
static char *in_file;
-unsigned long op[MAX_OPERANDS];
-int num_op;
+static char *out_file;
+static unsigned long op[MAX_OPERANDS];
-inline void debug(int level, const char *format, ...)
+/* Whether this instruction stores something in register */
+static int write_to_reg;
+
+static int out_lines = 0;
+
+void debug(int level, const char *format, ...)
{
#if DEBUG
char *p;
@@ -61,84 +54,39 @@
#endif
}
-/* Whether this instruction stores something in register */
-static int write_to_reg = 0;
+static int shift_fprintf(int level, FILE *f, const char *fmt, ...)
+{
+ va_list ap;
+ int i;
-static int olevel;
+ va_start(ap, fmt);
+ for(i = 0; i < level; i++)
+ fprintf(f, " ");
-/* Following functions recursivelly searches for substrings eval_operand and
- set_operand (see functions with the same name in execute.c) and replaces
- them with optimized code. */
-char *replace_operands (FILE *fo, char *str) {
- int replace = 0;
- if (*str == '}') {olevel--;}
- else if (*str == '{') {olevel++;}
- else if (strncmp ("eval_operand", str, 12) == 0) {
- replace = 1; str += 12;
- } else if (strncmp ("set_operand", str, 11) == 0) {
- replace = 2; str += 11;
- } else if (strncmp ("get_operand", str, 11) == 0) {
- replace = 10; str += 11;
- }
- if (replace) {
- int width, oper;
- if (replace < 10) {
- sscanf (str, "%i(%i", &width, &oper);
- while (*str && *str != '(') str++;
- while (*str && *str != ',') str++;
- str++;
- } else {
- sscanf (str, "(%i)", &oper);
- while (*str && *str != ')') str++;
- }
- if (replace == 1) {
- if (op[oper] & OPTYPE_DIS) {
- fprintf (fo, "eval_mem%i (%c", width, 'a' + oper);
- } else {
- if (op[oper] & OPTYPE_REG) {
- fprintf (fo, "(reg[%c]", 'a' + oper);
- } else {
- fprintf (fo, "(%c", 'a' + oper);
- }
- }
- } else if (replace == 2) {
- op[oper] |= OPTYPE_DST;
- if (op[oper] & OPTYPE_DIS) {
- fprintf (fo, "set_mem%i(%c,", width, 'a' + oper);
- } else if (op[oper] & OPTYPE_REG) {
- fprintf (fo, "reg[%c] = (", 'a' + oper);
- write_to_reg = 1;
- } else {
- fprintf (stderr, "Invalid operand type.\n");
- exit (1);
- }
- while (*str != ',') str = replace_operands (fo, str) + 1;
- } else {
- fprintf (fo, "%c", 'a' + oper);
- }
- if (replace < 10) {
- while (*str && *str != ')') str++;
- if (op[oper] & OPTYPE_DIS) fprintf (fo, ", &breakpoint)");
- else fprintf (fo, ")");
- }
- } else {
- fputc (*str, fo);
- }
- return str;
+ i = vfprintf(f, fmt, ap);
+ va_end(ap);
+
+ out_lines++;
+ return i + (level * 2);
}
/* Generates a execute sequence for one instruction */
int output_function (FILE *fo, const char *func_name, int level)
{
FILE *fi;
+ int olevel;
+ int line_num = 0;
+
if ((fi = fopen (in_file, "rt")) == NULL) {
printf("could not open file\n");
return 1;
- };
+ }
+
while (!feof (fi)) {
char line[10000], *str = line;
fgets (str, sizeof (line), fi);
- line[sizeof(line) - 1] = 0;
+ line[sizeof (line) - 1] = 0;
+ line_num++;
if (strncmp (str, "INSTRUCTION (", 13) == 0) {
char *s;
str += 13;
@@ -157,27 +105,25 @@
*s = 0;
while (isspace(*(s - 1))) s--;
*s = 0;
- fprintf (fo, "%s", str);
- fprintf (fo, " /* \"%s\" */\n", func_name);
- SHIFT;
+ /*shift_fprintf (level, fo, "#line %i \"%s\"\n", line_num, in_file);*/
+ shift_fprintf (level, fo, "%s", str);
+ shift_fprintf (level, fo, " /* \"%s\" */\n", func_name);
do {
fgets (line, sizeof (line), fi);
line[sizeof(line) - 1] = 0;
for (str = line; *str; str++) {
- str = replace_operands (fo, str);
+ if (*str == '{') olevel++;
+ else if (*str == '}') olevel--;
}
- SHIFT;
+ shift_fprintf (level, fo, "%s", line);
} while (olevel);
fclose(fi);
+ /*shift_fprintf (level, fo, "#line %i \"%s\"\n", out_lines, out_file);*/
return 0;
}
}
}
- fprintf (fo, "{\n");
- level++;
- SHIFT; fprintf (fo, "%s ();\n", func_name);
- level--;
- SHIFT; fprintf (fo, "}");
+ shift_fprintf (level, fo, "%s ();\n", func_name);
fclose(fi);
return 0;
@@ -186,117 +132,170 @@
/* Parses and puts operands into op[] structure.
Replacement for eval_operands routine. */
-static void
+static int
gen_eval_operands (FILE *fo, int insn_index, int level)
{
struct insn_op_struct *opd = op_start[insn_index];
+ int i;
+ int num_ops;
+ int nbits = 0;
+ int set_param = 0;
int dis = 0;
- int no = 0;
- int firstd = 1;
+ int sbit;
- while (1)
- {
- int nbits = 0, first = 1;
- while (1)
- {
- SHIFT;
- fprintf (fo, "tmp %s= ((insn >> %li) & 0x%08x) << %i;\n",
- first ? "" : "|", opd->type & OPTYPE_SHR,
- (1 << opd->data) - 1, nbits);
- nbits += opd->data;
- if (opd->type & OPTYPE_OP)
+ write_to_reg = 0;
+
+ shift_fprintf (level, fo, "unsigned long ");
+
+ /* Count number of operands */
+ for (i = 0, num_ops = 0;; i++) {
+ if (!(opd[i].type & OPTYPE_OP))
+ continue;
+ if (opd[i].type & OPTYPE_DIS)
+ continue;
+ if (num_ops)
+ fprintf(fo, ", ");
+ fprintf(fo, "%c", 'a' + num_ops);
+ num_ops++;
+ if (opd[i].type & OPTYPE_LAST)
break;
- opd++;
- first = 0;
}
- /* Do we have to sign extend? */
- if (opd->type & OPTYPE_SIG)
- {
- int sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;
- SHIFT; fprintf (fo, "if (tmp & (1 << %i)) tmp |= 0xFFFFFFFF << %i; /* Sign extend */\n", sbit, sbit);
- }
+ fprintf (fo, ";\n");
+
+ shift_fprintf (level, fo, "/* Number of operands: %i */\n", num_ops);
+
+ i = 0;
+ num_ops = 0;
+ do {
+/*
+ printf("opd[%i].type<last> = %c\n", i, opd->type & OPTYPE_LAST ? '1' : '0'); printf("opd[%i].type<op> = %c\n", i, opd->type & OPTYPE_OP ? '1' : '0');
+ printf("opd[%i].type<reg> = %c\n", i, opd->type & OPTYPE_REG ? '1' : '0');
+ printf("opd[%i].type<sig> = %c\n", i, opd->type & OPTYPE_SIG ? '1' : '0');
+ printf("opd[%i].type<dis> = %c\n", i, opd->type & OPTYPE_DIS ? '1' : '0');
+ printf("opd[%i].type<shr> = %i\n", i, opd->type & OPTYPE_SHR);
+ printf("opd[%i].type<sbit> = %i\n", i, (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR);
+ printf("opd[%i].data = %i\n", i, opd->data);
+*/
+
+ if (!nbits)
+ shift_fprintf (level, fo, "%c = (insn >> %i) & 0x%x;\n", 'a' + num_ops,
+ opd->type & OPTYPE_SHR, (1 << opd->data) - 1);
+ else
+ shift_fprintf (level, fo, "%c |= ((insn >> %i) & 0x%x) << %i;\n",
+ 'a' + num_ops, opd->type & OPTYPE_SHR,
+ (1 << opd->data) - 1, nbits);
+
+ nbits += opd->data;
+
if (opd->type & OPTYPE_DIS) {
- /* We have to read register later. */
- SHIFT; fprintf (fo, "data %s= tmp;\n", firstd ? "" : "+");
- firstd = 0;
+ sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;
+ if (opd->type & OPTYPE_SIG)
+ shift_fprintf (level, fo, "if(%c & 0x%08x) %c |= 0x%x;\n",
+ 'a' + num_ops, 1 << sbit, 'a' + num_ops,
+ 0xffffffff << sbit);
+ opd++;
+ shift_fprintf (level, fo, "(signed)%c += (signed)reg[(insn >> %i) & 0x%x];\n",
+ 'a' + num_ops, opd->type & OPTYPE_SHR,
+ (1 << opd->data) - 1);
dis = 1;
- } else
- {
- if (dis && (opd->type & OPTYPE_REG)) {
- if (MAX_GPRS == (1 << nbits)) {
- SHIFT; fprintf (fo, "%c = data + reg [tmp];\n", 'a' + no);
- } else {
- SHIFT; fprintf (fo, "%c = data + eval_reg32 (tmp);\n", 'a' + no);
}
+
+ if (opd->type & OPTYPE_OP) {
+ sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;
+ if (opd->type & OPTYPE_SIG)
+ shift_fprintf (level, fo, "if(%c & 0x%08x) %c |= 0x%x;\n",
+ 'a' + num_ops, 1 << sbit, 'a' + num_ops,
+ 0xffffffff << sbit);
+ if ((opd->type & OPTYPE_REG) && !dis) {
+ if(!i) {
+ shift_fprintf (level, fo, "#define SET_PARAM0(val) reg[a] = val\n");
+ set_param = 1;
+ }
+ shift_fprintf (level, fo, "#define PARAM%i reg[%c]\n", num_ops,
+ 'a' + num_ops);
+ if(opd->type & OPTYPE_DST)
+ write_to_reg = 1;
} else {
- SHIFT; fprintf (fo, "%c = tmp;\n", 'a' + no);
+ shift_fprintf (level, fo, "#define PARAM%i %c\n", num_ops,
+ 'a' + num_ops);
}
- op[no] = opd->type | (dis ? OPTYPE_DIS : 0);
- no++;
- firstd = 1;
+
+ op[num_ops] = opd->type;
+ if(dis)
+ op[num_ops] |= OPTYPE_DIS;
+ num_ops++;
+ nbits = 0;
dis = 0;
}
- if(opd->type & OPTYPE_LAST) goto last;
+
+ if ((opd->type & OPTYPE_LAST))
+ break;
opd++;
- }
+ i++;
+ } while (1);
+
+ output_function (fo, or32_opcodes[insn_index].function_name, level);
-last:
- num_op = no;
+ if (set_param)
+ shift_fprintf (level, fo, "#undef SET_PARAM\n");
+
+ for (i = 0; i < num_ops; i++)
+ shift_fprintf (level, fo, "#undef PARAM%i\n", i);
+
+ return num_ops;
}
/* Generates decode and execute for one instruction instance */
-int output_call (FILE *fo, int index, int level)
+static int output_call (FILE *fo, int index, int level)
{
int i;
- printf ("%i:%s\n", index, insn_name (index));
- fprintf (fo, "{\n");
- level++;
- if (index >= 0) {
- SHIFT; fprintf (fo, "unsigned long data, tmp;\n");
- SHIFT; fprintf (fo, "unsigned long a, b, c, d, e; /* operands */\n");
- }
- write_to_reg = 0;
+ int num_op;
+
+ /*printf ("%i:%s\n", index, insn_name (index));*/
+
+ shift_fprintf (level++, fo, "{\n");
+
if (index >= 0)
- gen_eval_operands (fo, index, level);
+ num_op = gen_eval_operands (fo, index, level);
else
num_op = 0;
- SHIFT;
+
if (index < 0) output_function (fo, "l_invalid", level);
- else output_function (fo, or32_opcodes[index].function_name, level);
+
fprintf (fo, "\n");
- SHIFT; fprintf (fo, "if (do_stats) {\n");
- level++;
- SHIFT; fprintf (fo, "num_op = %i;\n", num_op);
- if (num_op) {SHIFT; fprintf (fo, " op = ¤t->op[0];\n");}
- SHIFT; fprintf (fo, "current->insn_index = %i; /* \"%s\" */\n", index, insn_name (index));
+ shift_fprintf (level++, fo, "if (do_stats) {\n");
+ shift_fprintf (level, fo, "num_op = %i;\n", num_op);
+
+ if (num_op) shift_fprintf (level, fo, "op = ¤t->op[0];\n");
+ shift_fprintf (level, fo, "current->insn_index = %i; /* \"%s\" */\n", index,
+ insn_name (index));
+
for (i = 0; i < num_op; i++) {
- SHIFT; fprintf (fo, "op[%i] = %c;\n", i, 'a' + i);
- SHIFT; fprintf (fo, "op[%i + MAX_OPERANDS] = 0x%08x;\n", i, op[i]);
- }
- SHIFT; fprintf (fo, "analysis(current);\n");
- level--;
- SHIFT; fprintf (fo, "}\n");
- if (write_to_reg) {
- SHIFT; fprintf (fo, "reg[0] = 0; /* Repair in case we changed it */\n");
+ shift_fprintf (level, fo, "op[%i] = %c;\n", i, 'a' + i);
+ shift_fprintf (level, fo, "op[%i + MAX_OPERANDS] = 0x%08x;\n", i, op[i]);
}
- level--;
- SHIFT; fprintf (fo, "}");
+ shift_fprintf (level, fo, "analysis(current);\n");
+ shift_fprintf (--level, fo, "}\n");
+ if (write_to_reg)
+ shift_fprintf (level, fo, "reg[0] = 0; /* Repair in case we changed it */\n");
+ shift_fprintf (--level, fo, "}\n");
return 0;
}
/* Generates .c file header */
-int generate_header (FILE *fo)
+static int generate_header (FILE *fo)
{
fprintf (fo, "/* This file was automatically generated by generate (see cpu/or32/generate.c) */\n\n");
fprintf (fo, "static inline void decode_execute (struct iqueue_entry *current)\n{\n");
fprintf (fo, " unsigned long insn = current->insn;\n");
+ out_lines = 5;
return 0;
}
/* Generates .c file footer */
-int generate_footer (FILE *fo)
+static int generate_footer (FILE *fo)
{
fprintf (fo, "}\n");
return 0;
@@ -306,60 +305,58 @@
is similar to insn_decode, except it decodes all instructions. */
static int generate_body (FILE *fo, unsigned long *a, unsigned long cur_mask, int level)
{
+ unsigned long shift = *a;
+ unsigned long mask;
int i;
- if (!(*a & LEAF_FLAG)) {
- unsigned int shift = *a++;
- unsigned int mask = *a++;
- int prev_invalid = 0;
- fprintf (fo, "\n");
- SHIFT; fprintf (fo, "/* (insn >> %i) & 0x%x */\n", shift, mask);
- SHIFT; fprintf (fo, "switch ((insn >> %i) & 0x%x) {\n", shift, mask);
- level++;
+ int prev_inv = 0;
- /* Print each case recursively */
+ if (!(*a & LEAF_FLAG)) {
+ shift = *a++;
+ mask = *a++;
+ shift_fprintf (level, fo, "switch((insn >> %i) & 0x%x) {\n", shift,
+ mask);
for (i = 0; i <= mask; i++, a++) {
- /* Group invalid instruction decodes together */
if (!*a) {
- if (prev_invalid) fprintf (fo, "\n");
- prev_invalid = 1;
- SHIFT; fprintf (fo, "case 0x%02x: ", i);
+ shift_fprintf (level, fo, "case 0x%x:\n", i);
+ prev_inv = 1;
} else {
- if (prev_invalid) {
- if (output_call (fo, -1, level)) return 1;
- fprintf (fo, " break;\n");
- }
- SHIFT; fprintf (fo, "case 0x%02x: ", i);
- if (generate_body (fo, automata + *a, cur_mask | (mask << shift), level + 1)) return 1;
- prev_invalid = 0;
- }
- }
- if (prev_invalid) {
- if (output_call (fo, -1, level)) return 1;
- fprintf (fo, " break;\n");
- }
- level--;
- if (level > 1)
- fprintf (fo, "} break;\n");
- else
- fprintf (fo, "}\n");
+ if(prev_inv) {
+ shift_fprintf (++level, fo, "/* Invalid instruction(s) */\n");
+ shift_fprintf (level--, fo, "break;\n");
+ }
+ shift_fprintf (level, fo, "case 0x%x:\n", i);
+ generate_body (fo, automata + *a, cur_mask | (mask << shift), ++level);
+ shift_fprintf (level--, fo, "break;\n");
+ prev_inv = 0;
+ }
+ }
+ if (prev_inv) {
+ shift_fprintf (++level, fo, "/* Invalid instruction(s) */\n");
+ shift_fprintf (level--, fo, "break;\n");
+ }
+ shift_fprintf (level, fo, "}\n");
} else {
i = *a & ~LEAF_FLAG;
+
/* Final check - do we have direct match?
(based on or32_opcodes this should be the only possibility,
but in case of invalid/missing instruction we must perform a check) */
if (ti[i].insn_mask != cur_mask) {
- fprintf (fo, "\n");
- SHIFT;
- fprintf (fo, "/* Not unique: real mask %08lx and current mask %08lx differ - do final check */\n", ti[i].insn_mask, cur_mask);
- SHIFT; fprintf (fo, "if ((insn & 0x%08lx) == 0x%08lx) ", ti[i].insn_mask, ti[i].insn);
- if (output_call (fo, i, level)) return 1; // Fail
- fprintf (fo, " else ");
- if (output_call (fo, -1, level)) return 1; // Fail
- } else {
- if (output_call (fo, i, level - 1)) return 1; // Fail
+ shift_fprintf (level, fo, "/* Not unique: real mask %08lx and current mask %08lx differ - do final check */\n", ti[i].insn_mask, cur_mask);
+ shift_fprintf (level++, fo, "if((insn & 0x%x) == 0x%x) {\n",
+ ti[i].insn_mask, ti[i].insn);
+ }
+ shift_fprintf (level, fo, "/* Instruction: %s */\n", or32_opcodes[i].name);
+
+ output_call (fo, i, level);
+
+ if (ti[i].insn_mask != cur_mask) {
+ shift_fprintf (--level, fo, "} else {\n");
+ shift_fprintf (++level, fo, "/* Invalid insn */\n");
+ output_call (fo, -1, level);
+ shift_fprintf (--level, fo, "}\n");
}
- fprintf (fo, " break;\n");
}
return 0;
}
@@ -376,15 +373,28 @@
}
in_file = argv[1];
+ out_file = argv[2];
if (!(fo = fopen (argv[2], "wt+"))) {
fprintf (stderr, "Cannot create '%s'.\n", argv[2]);
exit (1);
}
build_automata ();
- if (generate_header (fo)) {fprintf (stderr, "generate_header\n"); return 1;}
- if (generate_body (fo, automata, 0, 1)) {fprintf (stderr, "generate_body\n"); return 1;}
- if (generate_footer (fo)) {fprintf (stderr, "generate_footer\n"); return 1;}
+ if (generate_header (fo)) {
+ fprintf (stderr, "generate_header\n");
+ return 1;
+ }
+
+ if (generate_body (fo, automata, 0, 1)) {
+ fprintf (stderr, "generate_body\n");
+ return 1;
+ }
+
+ if (generate_footer (fo)) {
+ fprintf (stderr, "generate_footer\n");
+ return 1;
+ }
+
fclose (fo);
destruct_automata ();
return 0;
1.39 +16 -9 or1k/or1ksim/cpu/or32/or32.c
http://www.opencores.org/cvsweb.shtml/or1k/or1ksim/cpu/or32/or32.c.diff?r1=1.38&r2=1.39
(In the diff below, changes in quantity of whitespace are not shown.)
Index: or32.c
===================================================================
RCS file: /cvsroot/nogj/or1k/or1ksim/cpu/or32/or32.c,v
retrieving revision 1.38
retrieving revision 1.39
diff -u -b -r1.38 -r1.39
--- or32.c 27 Jan 2005 13:15:50 -0000 1.38
+++ or32.c 27 Jan 2005 13:35:40 -0000 1.39
@@ -20,6 +20,10 @@
/*
* $Log: or32.c,v $
+ * Revision 1.39 2005/01/27 13:35:40 nogj
+ * * Fix generate.c to produce a execgen.c with less warnings.
+ * * Fix the --enable-simple configure option.
+ *
* Revision 1.38 2005/01/27 13:15:50 nogj
* Mark wich operand is the destination operand in the architechture definition
*
@@ -46,8 +50,6 @@
*
*/
-/* We treat all letters the same in encode/decode routines so
- we need to assign some characteristics to them like signess etc.*/
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
@@ -57,10 +59,15 @@
#ifdef HAVE_CONFIG_H
# include "config.h"
#endif
+#ifdef HAS_EXECUTION
+# include "abstract.h" /* To get struct iqueue_entry */
+#endif
#include "opcode/or32.h"
/* **INDENT-OFF** */
+/* We treat all letters the same in encode/decode routines so
+ we need to assign some characteristics to them like signess etc.*/
CONST struct or32_letter or32_letters[] =
{
{ 'A', NUM_UNSIGNED },
@@ -453,10 +460,17 @@
return "???";
}
+#if defined(HAS_EXECUTION) && SIMPLE_EXECUTION
+void
+l_none(struct iqueue_entry *current)
+{
+}
+#else
void
l_none()
{
}
+#endif
/*** Finite automata for instruction decoding building code ***/
@@ -497,7 +511,6 @@
#define MAX_AUTOMATA_SIZE (1200)
#define MAX_OP_TABLE_SIZE (1200)
-#define LEAF_FLAG (0x80000000)
#define MAX_LEN (8)
#ifndef MIN
@@ -509,12 +522,7 @@
int curpass = 0;
/* MM: Struct that holds runtime build information about instructions. */
-struct temp_insn_struct
-{
- unsigned long insn;
- unsigned long insn_mask;
- int in_pass;
-} *ti;
+struct temp_insn_struct *ti;
struct insn_op_struct *op_data, **op_start;
1.98 +23 -82 or1k/or1ksim/cpu/or32/execute.c
http://www.opencores.org/cvsweb.shtml/or1k/or1ksim/cpu/or32/execute.c.diff?r1=1.97&r2=1.98
(In the diff below, changes in quantity of whitespace are not shown.)
Index: execute.c
===================================================================
RCS file: /cvsroot/nogj/or1k/or1ksim/cpu/or32/execute.c,v
retrieving revision 1.97
retrieving revision 1.98
diff -u -b -r1.97 -r1.98
--- execute.c 15 Oct 2004 22:53:00 -0000 1.97
+++ execute.c 27 Jan 2005 13:35:42 -0000 1.98
@@ -29,7 +29,6 @@
#include "config.h"
#include "arch.h"
-#include "opcode/or32.h"
#include "branch_predict.h"
#include "abstract.h"
#include "labels.h"
@@ -44,6 +43,7 @@
#include "immu.h"
#include "dmmu.h"
#include "debug.h"
+#include "opcode/or32.h"
/* General purpose registers. */
machword reg[MAX_GPRS];
@@ -611,7 +611,11 @@
}
/* If decoding cannot be found, call this function */
+#if SIMPLE_EXECUTION
+void l_invalid (struct iqueue_entry *current) {
+#else
void l_invalid () {
+#endif
/* It would be hard to handle this case for statistics; we skip it
since it should not occur anyway:
IFF (config.cpu.dependstats) current->func_unit = it_unknown; */
@@ -626,8 +630,7 @@
#else /* SIMPLE_EXECUTION */
-#define INSTRUCTION(name) void name ()
-#define get_operand (op_no) op[(op_no)]
+#define INSTRUCTION(name) void name (struct iqueue_entry *current)
/* Implementation specific.
Parses and returns operands. */
@@ -686,96 +689,28 @@
/* Implementation specific.
Evaluates source operand op_no. */
-inline static unsigned long eval_operand32 (int op_no, int *breakpoint)
-{
- if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)
- /* memory accesses are not cached */
- return eval_mem32 (op[op_no], breakpoint);
- else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {
- return eval_reg32 (op[op_no]);
- } else {
- return op[op_no];
- }
-}
-
-/* Implementation specific.
- Evaluates source operand op_no. */
-
-static unsigned long eval_operand16 (int op_no, int *breakpoint)
+static unsigned long eval_operand (int op_no)
{
if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
- return eval_mem16 (op[op_no], breakpoint);
- }
- else {
- fprintf (stderr, "Invalid operand type.\n");
- exit (1);
- }
-}
-
-/* Implementation specific.
- Evaluates source operand op_no. */
-
-static unsigned long eval_operand8 (int op_no, int *breakpoint)
-{
- if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)
- return eval_mem8 (op[op_no], breakpoint);
- else {
- fprintf (stderr, "Invalid operand type.\n");
- exit (1);
- }
-}
-
-/* Implementation specific.
- Set destination operand (register direct, register indirect
- (with displacement) with value. */
-
-inline static void set_operand32(int op_no, unsigned long value, int* breakpoint)
-{
- /* Mark this as destination operand. */
- IFF (config.cpu.dependstats) op[op_no + MAX_OPERANDS] |= OPTYPE_DST;
- if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
- set_mem32(op[op_no], value, breakpoint);
+ return op[op_no];
} else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {
- set_reg32(op[op_no], value);
+ return eval_reg32 (op[op_no]);
} else {
- fprintf (stderr, "Invalid operand type.\n");
- exit (1);
- }
-}
-
-/* Implementation specific.
- Set destination operand (register direct, register indirect
- (with displacement) with value. */
-
-void set_operand16(int op_no, unsigned long value, int* breakpoint)
-{
- /* Mark this as destination operand. */
- op[op_no + MAX_OPERANDS] |= OPTYPE_DST;
- if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
- set_mem16(op[op_no], value, breakpoint);
- }
- else
- {
- fprintf (stderr, "Invalid operand type.\n");
- exit (1);
+ return op[op_no];
}
}
/* Implementation specific.
- Set destination operand (register direct, register indirect
- (with displacement) with value. */
+ Set destination operand (reister direct) with value. */
-void set_operand8(int op_no, unsigned long value, int* breakpoint)
+inline static void set_operand(int op_no, unsigned long value)
{
/* Mark this as destination operand. */
- op[op_no + MAX_OPERANDS] |= OPTYPE_DST;
- if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)
- set_mem8(op[op_no], value, breakpoint);
- else
- {
- fprintf (stderr, "Invalid operand type.\n");
+ if (!(op[op_no + MAX_OPERANDS] & OPTYPE_REG)) {
+ fprintf (stderr, "Trying to set a non-register operand\n");
exit (1);
}
+ set_reg32(op[op_no], value);
}
/* Simple and rather slow decoding function based on built automata. */
@@ -786,15 +721,21 @@
current->insn_index = insn_index = insn_decode(current->insn);
if (insn_index < 0)
- l_invalid();
+ l_invalid(current);
else {
op = ¤t->op[0];
eval_operands (current->insn, insn_index, &breakpoint);
- or32_opcodes[insn_index].exec();
+ or32_opcodes[insn_index].exec(current);
}
if (do_stats) analysis(&iqueue[0]);
}
+#define SET_PARAM0(val) set_operand(0, val)
+
+#define PARAM0 eval_operand(0)
+#define PARAM1 eval_operand(1)
+#define PARAM2 eval_operand(2)
+
#include "insnset.c"
#endif /* !SIMPLE_EXECUTION */
1.15 +128 -101 or1k/or1ksim/cpu/or32/insnset.c
http://www.opencores.org/cvsweb.shtml/or1k/or1ksim/cpu/or32/insnset.c.diff?r1=1.14&r2=1.15
(In the diff below, changes in quantity of whitespace are not shown.)
Index: insnset.c
===================================================================
RCS file: /cvsroot/nogj/or1k/or1ksim/cpu/or32/insnset.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -b -r1.14 -r1.15
--- insnset.c 11 Jan 2005 15:41:58 -0000 1.14
+++ insnset.c 27 Jan 2005 13:35:44 -0000 1.15
@@ -23,10 +23,10 @@
signed char temp4;
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- temp2 = (signed long)eval_operand32(2, &breakpoint);
- temp3 = (signed long)eval_operand32(1, &breakpoint);
+ temp2 = (signed long)PARAM2;
+ temp3 = (signed long)PARAM1;
temp1 = temp2 + temp3;
- set_operand32(0, temp1, &breakpoint);
+ SET_PARAM0(temp1);
set_ov_flag (temp1);
if (ARITH_SET_FLAG) {
flag = temp1 == 0;
@@ -46,10 +46,10 @@
signed char temp4;
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- temp2 = (signed long)eval_operand32(2, &breakpoint);
- temp3 = (signed long)eval_operand32(1, &breakpoint);
+ temp2 = (signed long)PARAM2;
+ temp3 = (signed long)PARAM1;
temp1 = temp2 + temp3 + getsprbits(SPR_SR, SPR_SR_CY);
- set_operand32(0, temp1, &breakpoint);
+ SET_PARAM0(temp1);
set_ov_flag (temp1);
if (ARITH_SET_FLAG) {
flag = temp1 == 0;
@@ -68,7 +68,7 @@
int old_cyc = 0;
IFF (config.cpu.dependstats) current->func_unit = it_store;
IFF (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
- set_operand32(0, eval_operand32(1, &breakpoint), &breakpoint);
+ set_mem32(PARAM0, PARAM1, &breakpoint);
if (config.cpu.sbuf_len) {
int t = runtime.sim.mem_cycles;
runtime.sim.mem_cycles = old_cyc;
@@ -79,7 +79,7 @@
int old_cyc = 0;
IFF (config.cpu.dependstats) current->func_unit = it_store;
IFF (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
- set_operand8(0, eval_operand32(1, &breakpoint), &breakpoint);
+ set_mem8(PARAM0, PARAM1, &breakpoint);
if (config.cpu.sbuf_len) {
int t = runtime.sim.mem_cycles;
runtime.sim.mem_cycles = old_cyc;
@@ -90,7 +90,7 @@
int old_cyc = 0;
IFF (config.cpu.dependstats) current->func_unit = it_store;
IFF (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
- set_operand16(0, eval_operand32(1, &breakpoint), &breakpoint);
+ set_mem16(PARAM0, PARAM1, &breakpoint);
if (config.cpu.sbuf_len) {
int t = runtime.sim.mem_cycles;
runtime.sim.mem_cycles = old_cyc;
@@ -101,78 +101,92 @@
unsigned long val;
IFF (config.cpu.dependstats) current->func_unit = it_load;
if (config.cpu.sbuf_len) sbuf_load ();
- val = eval_operand32(1, &breakpoint);
+ val = eval_mem32(PARAM1, &breakpoint);
/* If eval operand produced exception don't set anything */
if (!pending.valid)
- set_operand32(0, val, &breakpoint);
+ SET_PARAM0(val);
}
INSTRUCTION (l_lbs) {
signed char val;
IFF (config.cpu.dependstats) current->func_unit = it_load;
if (config.cpu.sbuf_len) sbuf_load ();
- val = eval_operand8(1, &breakpoint);
+ val = eval_mem8(PARAM1, &breakpoint);
/* If eval opreand produced exception don't set anything */
if (!pending.valid)
- set_operand32(0, val, &breakpoint);
+ SET_PARAM0(val);
}
INSTRUCTION (l_lbz) {
unsigned char val;
IFF (config.cpu.dependstats) current->func_unit = it_load;
if (config.cpu.sbuf_len) sbuf_load ();
- val = eval_operand8(1, &breakpoint);
+ val = eval_mem8(PARAM1, &breakpoint);
/* If eval opreand produced exception don't set anything */
if (!pending.valid)
- set_operand32(0, val, &breakpoint);
+ SET_PARAM0(val);
}
INSTRUCTION (l_lhs) {
signed short val;
IFF (config.cpu.dependstats) current->func_unit = it_load;
if (config.cpu.sbuf_len) sbuf_load ();
- val = eval_operand16(1, &breakpoint);
+ val = eval_mem16(PARAM1, &breakpoint);
/* If eval opreand produced exception don't set anything */
if (!pending.valid)
- set_operand32(0, val, &breakpoint);
+ SET_PARAM0(val);
}
INSTRUCTION (l_lhz) {
unsigned short val;
IFF (config.cpu.dependstats) current->func_unit = it_load;
if (config.cpu.sbuf_len) sbuf_load ();
- val = eval_operand16(1, &breakpoint);
+ val = eval_mem16(PARAM1, &breakpoint);
/* If eval opreand produced exception don't set anything */
if (!pending.valid)
- set_operand32(0, val, &breakpoint);
+ SET_PARAM0(val);
}
INSTRUCTION (l_movhi) {
IFF (config.cpu.dependstats) current->func_unit = it_movimm;
- set_operand32(0, eval_operand32(1, &breakpoint) << 16, &breakpoint);
+ SET_PARAM0(PARAM1 << 16);
}
INSTRUCTION (l_and) {
unsigned long temp1;
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- set_operand32(0, temp1 = set_ov_flag (eval_operand32(1, &breakpoint) & (unsigned)eval_operand32(2, &breakpoint)), &breakpoint);
+ temp1 = PARAM1 & PARAM2;
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
if (ARITH_SET_FLAG) {
flag = temp1 == 0;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
}
INSTRUCTION (l_or) {
+ unsigned long temp1;
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) | (unsigned)eval_operand32(2, &breakpoint)), &breakpoint);
+ temp1 = PARAM1 | PARAM2;
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
}
INSTRUCTION (l_xor) {
+ unsigned long temp1;
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) ^ (signed)eval_operand32(2, &breakpoint)), &breakpoint);
+ temp1 = PARAM1 ^ PARAM2;
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
}
INSTRUCTION (l_sub) {
+ signed long temp1;
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- set_operand32(0, set_ov_flag ((signed long)eval_operand32(1, &breakpoint) - (signed long)eval_operand32(2, &breakpoint)), &breakpoint);
+ temp1 = (signed long)PARAM1 - (signed long)PARAM2;
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
}
/*int mcount = 0;*/
INSTRUCTION (l_mul) {
- signed long temp3, temp2, temp1;
+ signed long temp1;
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- set_operand32(0, set_ov_flag ((signed long)eval_operand32(1, &breakpoint) * (signed long)eval_operand32(2, &breakpoint)), &breakpoint);
+
+ temp1 = PARAM1 * PARAM2;
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
/*if (!(mcount++ & 1023)) {
PRINTF ("[%i]\n",mcount);
}*/
@@ -181,57 +195,69 @@
signed long temp3, temp2, temp1;
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- temp3 = eval_operand32(2, &breakpoint);
- temp2 = eval_operand32(1, &breakpoint);
+ temp3 = PARAM2;
+ temp2 = PARAM1;
if (temp3)
temp1 = temp2 / temp3;
else {
except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
return;
}
- set_operand32(0, set_ov_flag (temp1), &breakpoint);
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
}
INSTRUCTION (l_divu) {
unsigned long temp3, temp2, temp1;
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- temp3 = eval_operand32(2, &breakpoint);
- temp2 = eval_operand32(1, &breakpoint);
+ temp3 = PARAM2;
+ temp2 = PARAM1;
+ if (temp3)
temp1 = temp2 / temp3;
+ else {
+ except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
+ return;
+ }
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
/* runtime.sim.cycles += 16; */
- set_operand32(0, set_ov_flag (temp1), &breakpoint);
}
INSTRUCTION (l_sll) {
- int sign = 1;
+ unsigned long temp1;
+
IFF (config.cpu.dependstats) current->func_unit = it_shift;
- if ((signed)eval_operand32(1, &breakpoint) < 0)
- sign = -1;
+
+ temp1 = PARAM1 << PARAM2;
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
/* runtime.sim.cycles += 2; */
- set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) << eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (l_sra) {
- unsigned long sign = 0;
+ signed long temp1;
IFF (config.cpu.dependstats) current->func_unit = it_shift;
- if ((signed)eval_operand32(1, &breakpoint) < 0)
- sign = -1;
+ temp1 = (signed)PARAM1 >> PARAM2;
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
/* runtime.sim.cycles += 2; */
- set_operand32(0, set_ov_flag ((signed)eval_operand32(1, &breakpoint) >> eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (l_srl) {
+ unsigned long temp1;
IFF (config.cpu.dependstats) current->func_unit = it_shift;
+ temp1 = PARAM1 >> PARAM2;
+ set_ov_flag (temp1);
+ SET_PARAM0(temp1);
/* runtime.sim.cycles += 2; */
- set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) >> eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (l_bf) {
if (config.bpb.enabled) {
- int fwd = (eval_operand32(0, &breakpoint) >= pc) ? 1 : 0;
+ int fwd = (PARAM0 >= pc) ? 1 : 0;
IFF (config.cpu.dependstats) current->func_unit = it_branch;
or1k_mstats.bf[flag][fwd]++;
bpb_update(current->insn_addr, flag);
}
if (flag) {
- pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
+ pcdelay = pc + (signed)PARAM0 * 4;
btic_update(pcnext);
next_delay_insn = 1;
} else {
@@ -240,13 +266,13 @@
}
INSTRUCTION (l_bnf) {
if (config.bpb.enabled) {
- int fwd = (eval_operand32(0, &breakpoint) >= pc) ? 1 : 0;
+ int fwd = (PARAM0 >= pc) ? 1 : 0;
IFF (config.cpu.dependstats) current->func_unit = it_branch;
or1k_mstats.bnf[!flag][fwd]++;
bpb_update(current->insn_addr, flag == 0);
}
if (flag == 0) {
- pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
+ pcdelay = pc + (signed)PARAM0 * 4;
btic_update(pcnext);
next_delay_insn = 1;
} else {
@@ -254,12 +280,12 @@
}
}
INSTRUCTION (l_j) {
- pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
+ pcdelay = pc + (signed)PARAM0 * 4;
IFF (config.cpu.dependstats) current->func_unit = it_jump;
next_delay_insn = 1;
}
INSTRUCTION (l_jal) {
- pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
+ pcdelay = pc + (signed)PARAM0 * 4;
IFF (config.cpu.dependstats) current->func_unit = it_jump;
set_reg32(LINK_REGNO, pc + 8);
@@ -268,20 +294,20 @@
struct mem_entry *entry;
struct label_entry *tmp;
if (verify_memoryarea(pcdelay) && (tmp = get_label (pcdelay)))
- fprintf (runtime.sim.fprof, "+%08X %08X %08X %s\n", runtime.sim.cycles, pc + 8, pcdelay, tmp->name);
+ fprintf (runtime.sim.fprof, "+%08X %08lX %08X %s\n", runtime.sim.cycles, pc + 8, pcdelay, tmp->name);
else
fprintf (runtime.sim.fprof, "+%08X %08X %08X @%08X\n", runtime.sim.cycles, pc + 8, pcdelay, pcdelay);
}
}
INSTRUCTION (l_jalr) {
IFF (config.cpu.dependstats) current->func_unit = it_jump;
- pcdelay = eval_operand32(0, &breakpoint);
+ pcdelay = PARAM0;
set_reg32(LINK_REGNO, pc + 8);
next_delay_insn = 1;
}
INSTRUCTION (l_jr) {
IFF (config.cpu.dependstats) current->func_unit = it_jump;
- pcdelay = eval_operand32(0, &breakpoint);
+ pcdelay = PARAM0;
next_delay_insn = 1;
if (config.sim.profile)
fprintf (runtime.sim.fprof, "-%08X %08X\n", runtime.sim.cycles, pcdelay);
@@ -293,7 +319,7 @@
}
INSTRUCTION (l_nop) {
unsigned long stackaddr;
- int k = eval_operand32(0, &breakpoint);
+ int k = PARAM0;
IFF (config.cpu.dependstats) current->func_unit = it_nop;
switch (k) {
case NOP_NOP:
@@ -302,7 +328,8 @@
PRINTF("exit(%d)\n", evalsim_reg32 (3));
fprintf(stderr, "@reset : cycles %lld, insn #%lld\n", runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
- fprintf(stderr, " diff : cycles %lld, insn #%lld\n", runtime.sim.cycles - runtime.sim.reset_cycles, runtime.cpu.instructions - runtime.cpu.reset_instructions);
+ fprintf(stderr, " diff : cycles %lld, insn #%lld\n", runtime.sim.cycles,
+ runtime.sim.reset_cycles, runtime.cpu.instructions - runtime.cpu.reset_instructions);
if (config.debug.gdb_enabled)
set_stall_state (1);
else
@@ -330,93 +357,93 @@
}
INSTRUCTION (l_sfeq) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = eval_operand32(0, &breakpoint) == eval_operand32(1, &breakpoint);
+ flag = PARAM0 == PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_sfne) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = eval_operand32(0, &breakpoint) != eval_operand32(1, &breakpoint);
+ flag = PARAM0 != PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_sfgts) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = (signed)eval_operand32(0, &breakpoint) > (signed)eval_operand32(1, &breakpoint);
+ flag = (signed)PARAM0 > (signed)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_sfges) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = (signed)eval_operand32(0, &breakpoint) >= (signed)eval_operand32(1, &breakpoint);
+ flag = (signed)PARAM0 >= (signed)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_sflts) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = (signed)eval_operand32(0, &breakpoint) < (signed)eval_operand32(1, &breakpoint);
+ flag = (signed)PARAM0 < (signed)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_sfles) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = (signed)eval_operand32(0, &breakpoint) <= (signed)eval_operand32(1, &breakpoint);
+ flag = (signed)PARAM0 <= (signed)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_sfgtu) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = (unsigned)eval_operand32(0, &breakpoint) > (unsigned)eval_operand32(1, &breakpoint);
+ flag = (unsigned)PARAM0 > (unsigned)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_sfgeu) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = (unsigned)eval_operand32(0, &breakpoint) >= (unsigned) eval_operand32(1, &breakpoint);
+ flag = (unsigned)PARAM0 >= (unsigned)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_sfltu) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = (unsigned)eval_operand32(0, &breakpoint) < (unsigned)eval_operand32(1, &breakpoint);
+ flag = (unsigned)PARAM0 < (unsigned)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_sfleu) {
IFF (config.cpu.dependstats) current->func_unit = it_compare;
- flag = (unsigned)eval_operand32(0, &breakpoint) <= (unsigned)eval_operand32(1, &breakpoint);
+ flag = (unsigned)PARAM0 <= (unsigned)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (l_extbs) {
unsigned char x;
IFF (config.cpu.dependstats) current->func_unit = it_move;
- x = eval_operand32(1, &breakpoint);
- set_operand32(0, (signed long)x, &breakpoint);
+ x = PARAM1;
+ SET_PARAM0((signed long)x);
}
INSTRUCTION (l_extbz) {
unsigned char x;
IFF (config.cpu.dependstats) current->func_unit = it_move;
- x = eval_operand32(1, &breakpoint);
- set_operand32(0, (unsigned long)x, &breakpoint);
+ x = PARAM1;
+ SET_PARAM0((unsigned long)x);
}
INSTRUCTION (l_exths) {
unsigned short x;
IFF (config.cpu.dependstats) current->func_unit = it_move;
- x = eval_operand32(1, &breakpoint);
- set_operand32(0, (signed long)x, &breakpoint);
+ x = PARAM1;
+ SET_PARAM0((signed long)x);
}
INSTRUCTION (l_exthz) {
unsigned short x;
IFF (config.cpu.dependstats) current->func_unit = it_move;
- x = eval_operand32(1, &breakpoint);
- set_operand32(0, (unsigned long)x, &breakpoint);
+ x = PARAM1;
+ SET_PARAM0((unsigned long)x);
}
INSTRUCTION (l_extws) {
unsigned int x;
IFF (config.cpu.dependstats) current->func_unit = it_move;
- x = eval_operand32(1, &breakpoint);
- set_operand32(0, (signed long)x, &breakpoint);
+ x = PARAM1;
+ SET_PARAM0((signed long)x);
}
INSTRUCTION (l_extwz) {
unsigned int x;
IFF (config.cpu.dependstats) current->func_unit = it_move;
- x = eval_operand32(1, &breakpoint);
- set_operand32(0, (unsigned long)x, &breakpoint);
+ x = PARAM1;
+ SET_PARAM0((unsigned long)x);
}
INSTRUCTION (l_mtspr) {
- unsigned long regno = eval_operand32(0, &breakpoint) + eval_operand32(2, &breakpoint);
- unsigned long value = eval_operand32(1, &breakpoint);
+ unsigned long regno = PARAM0 + PARAM2;
+ unsigned long value = PARAM1;
if (runtime.sim.fspr_log) {
fprintf(runtime.sim.fspr_log, "Write to SPR : [%08lX] <- [%08lX]\n", regno, value);
@@ -431,7 +458,7 @@
}
}
INSTRUCTION (l_mfspr) {
- unsigned long regno = eval_operand32(1, &breakpoint) + eval_operand32(2, &breakpoint);
+ unsigned long regno = PARAM1 + PARAM2;
unsigned long value = mfspr(regno);
if (runtime.sim.fspr_log) {
@@ -440,9 +467,9 @@
IFF (config.cpu.dependstats) current->func_unit = it_move;
if (mfspr(SPR_SR) & SPR_SR_SM)
- set_operand32(0, value, &breakpoint);
+ SET_PARAM0(value);
else {
- set_operand32(0, 0, &breakpoint);
+ SET_PARAM0(0);
PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
runtime.sim.cont_run = 0;
}
@@ -461,8 +488,8 @@
IFF (config.cpu.dependstats) current->func_unit = it_mac;
lo = mfspr (SPR_MACLO);
hi = mfspr (SPR_MACHI);
- x = eval_operand32(0, &breakpoint);
- y = eval_operand32(1, &breakpoint);
+ x = PARAM0;
+ y = PARAM1;
PRINTF ("[%08x,%08x]\t", (unsigned long)(x), (unsigned long)(y));
l = (ULONGEST)lo | ((LONGEST)hi << 32);
l += (LONGEST) x * (LONGEST) y;
@@ -481,11 +508,11 @@
IFF (config.cpu.dependstats) current->func_unit = it_mac;
lo = mfspr (SPR_MACLO);
hi = mfspr (SPR_MACHI);
- x = eval_operand32(0, &breakpoint);
- y = eval_operand32(1, &breakpoint);
+ x = PARAM0;
+ y = PARAM1;
PRINTF ("[%08x,%08x]\t", (unsigned long)(x), (unsigned long)(y));
l = (ULONGEST)lo | ((LONGEST)hi << 32);
- l -= (LONGEST) eval_operand32(0, &breakpoint) * (LONGEST)eval_operand32(1, &breakpoint);
+ l -= x * y;
/* This implementation is very fast - it needs only one cycle for msb. */
lo = ((ULONGEST)l) & 0xFFFFFFFF;
@@ -504,27 +531,27 @@
l = (ULONGEST) lo | ((LONGEST)hi << 32);
l >>= 28;
//PRINTF ("<%08x>\n", (unsigned long)l);
- set_operand32(0, (long)l, &breakpoint);
+ SET_PARAM0((long)l);
mtspr (SPR_MACLO, 0);
mtspr (SPR_MACHI, 0);
}
INSTRUCTION (l_cmov) {
IFF (config.cpu.dependstats) current->func_unit = it_move;
- set_operand32(0, flag ? eval_operand32(1, &breakpoint) : eval_operand32(2, &breakpoint), &breakpoint);
+ SET_PARAM0(flag ? PARAM1 : PARAM2);
}
INSTRUCTION (l_ff1) {
IFF (config.cpu.dependstats) current->func_unit = it_arith;
- set_operand32(0, ffs((unsigned long)eval_operand32(1, &breakpoint)) , &breakpoint);
+ SET_PARAM0(ffs(PARAM1));
}
/******* Floating point instructions *******/
/* Single precision */
INSTRUCTION (lf_add_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- set_operand32(0, (machword)((float)eval_operand32(1, &breakpoint) + (float)eval_operand32(2, &breakpoint)), &breakpoint);
+ SET_PARAM0((machword)((float)PARAM1 + (float)PARAM2));
}
INSTRUCTION (lf_div_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- set_operand32(0, (machword)((float)eval_operand32(1, &breakpoint) / (float)eval_operand32(2, &breakpoint)), &breakpoint);
+ SET_PARAM0((machword)((float)PARAM1 / (float)PARAM2));
}
INSTRUCTION (lf_ftoi_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
@@ -536,50 +563,50 @@
}
INSTRUCTION (lf_madd_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- set_operand32(0, (machword)((float)eval_operand32(0, &breakpoint) + (float)eval_operand32(1, &breakpoint) * (float)eval_operand32(2, &breakpoint)), &breakpoint);
+ SET_PARAM0((machword)((float)PARAM0 + (float)PARAM1 * (float)PARAM2));
}
INSTRUCTION (lf_mul_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- set_operand32(0, (machword)((float)eval_operand32(1, &breakpoint) * (float)eval_operand32(2, &breakpoint)), &breakpoint);
+ SET_PARAM0((machword)((float)PARAM1 * (float)PARAM2));
}
INSTRUCTION (lf_rem_s) {
- float temp = (float)eval_operand32(1, &breakpoint) / (float)eval_operand32(2, &breakpoint);
+ float temp = (float)PARAM1 / (float)PARAM2;
IFF (config.cpu.dependstats) current->func_unit = it_float;
- set_operand32(0, temp - (machword)temp, &breakpoint);
+ SET_PARAM0(temp - (machword)temp);
}
INSTRUCTION (lf_sfeq_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- flag = (float)eval_operand32(0, &breakpoint) == (float)eval_operand32(1, &breakpoint);
+ flag = (float)PARAM0 == (float)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sfge_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- flag = (float)eval_operand32(0, &breakpoint) >= (float)eval_operand32(1, &breakpoint);
+ flag = (float)PARAM0 >= (float)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sfgt_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- flag = (float)eval_operand32(0, &breakpoint) > (float)eval_operand32(1, &breakpoint);
+ flag = (float)PARAM0 > (float)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sfle_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- flag = (float)eval_operand32(0, &breakpoint) <= (float)eval_operand32(1, &breakpoint);
+ flag = (float)PARAM0 <= (float)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sflt_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- flag = (float)eval_operand32(0, &breakpoint) < (float)eval_operand32(1, &breakpoint);
+ flag = (float)PARAM0 < (float)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sfne_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- flag = (float)eval_operand32(0, &breakpoint) != (float)eval_operand32(1, &breakpoint);
+ flag = (float)PARAM0 != (float)PARAM1;
setsprbits(SPR_SR, SPR_SR_F, flag);
}
INSTRUCTION (lf_sub_s) {
IFF (config.cpu.dependstats) current->func_unit = it_float;
- set_operand32(0, (machword)((float)eval_operand32(1, &breakpoint) - (float)eval_operand32(2, &breakpoint)), &breakpoint);
+ SET_PARAM0((machword)((float)PARAM1 - (float)PARAM2));
}
/******* Custom instructions *******/
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