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From: OpenCores CVS Agent<cvs@o...>
Date: Thu Jan 20 14:49:41 CET 2005
Subject: [cvs-checkins] MODIFIED: usbhostslave ...
Date: 00/05/01 20:14:49

Modified: usbhostslave/RTL/wrapper usbHostSlave.v usbHostSlaveWrap.v
Log:
Fixed bus turn-around problems, added version number


Revision Changes Path
1.3 +9 -11 usbhostslave/RTL/wrapper/usbHostSlave.v

http://www.opencores.org/cvsweb.shtml/usbhostslave/RTL/wrapper/usbHostSlave.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: usbHostSlave.v
===================================================================
RCS file: /cvsroot/sfielding/usbhostslave/RTL/wrapper/usbHostSlave.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- usbHostSlave.v 18 Dec 2004 14:36:23 -0000 1.2
+++ usbHostSlave.v 20 Jan 2005 13:49:06 -0000 1.3
@@ -41,18 +41,7 @@
//// ////
//////////////////////////////////////////////////////////////////////
//
-// $Id: usbHostSlave.v,v 1.2 2004/12/18 14:36:23 sfielding Exp $
-//
-// CVS Revision History
-//
-// $Log: usbHostSlave.v,v $
-// Revision 1.2 2004/12/18 14:36:23 sfielding
-// Removed html documentation
-//
-// Revision 1.1.1.1 2004/10/11 04:01:11 sfielding
-// Created
-//
-//
+`timescale 1ns / 1ps

module usbHostSlave(
clk,
@@ -76,7 +65,8 @@
USBWireDataInTick,
USBWireDataOut,
USBWireDataOutTick,
- USBWireCtrlOut
+ USBWireCtrlOut,
+ USBFullSpeed
);
parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
parameter HOST_FIFO_ADDR_WIDTH = 6;
@@ -111,6 +101,7 @@
output USBWireDataOutTick;
output USBWireDataInTick;
output USBWireCtrlOut;
+output USBFullSpeed;

wire clk;
wire rst;
@@ -134,6 +125,7 @@
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireCtrlOut;
+wire USBFullSpeed;

//internal wiring
wire hostControlSel;
@@ -212,6 +204,8 @@
wire slaveEP2TxFifoSel;
wire slaveEP3TxFifoSel;

+assign USBFullSpeed = fullSpeedBitRateToSIE;
+
usbHostControl u_usbHostControl(
.clk(clk),
.rst(rst),
@@ -349,6 +343,7 @@
.fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
.dataIn(data_i),
.dataOut(dataFromHostSlaveMux),
+ .address(address_i[0]),
.writeEn(writeEn),
.strobe_i(strobe_i),
.clk(clk),



1.2 +5 -10 usbhostslave/RTL/wrapper/usbHostSlaveWrap.v

http://www.opencores.org/cvsweb.shtml/usbhostslave/RTL/wrapper/usbHostSlaveWrap.v.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: usbHostSlaveWrap.v
===================================================================
RCS file: /cvsroot/sfielding/usbhostslave/RTL/wrapper/usbHostSlaveWrap.v,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- usbHostSlaveWrap.v 18 Dec 2004 14:57:10 -0000 1.1
+++ usbHostSlaveWrap.v 20 Jan 2005 13:49:07 -0000 1.2
@@ -6,7 +6,7 @@ //// <http://www.opencores.org/cores//> //// //// //// //// Module Description: //// -//// Top level module wrapper. Enable connection to Avalon bus +//// Top level module wrapper. Enable connection to Altera Avalon bus //// //// //// To Do: //// //// @@ -41,16 +41,8 @@ //// //// ////////////////////////////////////////////////////////////////////// // -// $Id: usbHostSlaveWrap.v,v 1.1 2004/12/18 14:57:10 sfielding Exp $ -// -// CVS Revision History -// -// $Log: usbHostSlaveWrap.v,v $ -// Revision 1.1 2004/12/18 14:57:10 sfielding -// Added Altera wrapper -// -// -// +`timescale 1ns / 1ps + module usbHostSlaveWrap( clk, @@ -148,7 +140,6 @@ assign USBWireDataIn = {USBWireVPI, USBWireVMI}; assign {USBWireVPO, USBWireVMO} = USBWireDataOut; -assign USBFullSpeed = 1'b1; assign DPlusPullUp = 1'b1; assign DMinusPullUp = 1'bz; @@ -195,7 +186,8 @@ .USBWireDataInTick(USBWireDataInTick), .USBWireDataOut(USBWireDataOut), .USBWireDataOutTick(USBWireDataOutTick), - .USBWireCtrlOut(USBWireCtrlOut)); + .USBWireCtrlOut(USBWireCtrlOut), + .USBFullSpeed(USBFullSpeed)); endmodule