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From: OpenCores CVS Agent<cvs@o...>
Date: Thu Jan 20 14:41:16 CET 2005
Subject: [cvs-checkins] MODIFIED: usbhostslave ...
Date: 00/05/01 20:14:41

Modified: usbhostslave/RTL/hostSlaveMux hostSlaveMux.v
hostSlaveMuxBI.v
Log:
Fixed bus turn-around problems, added version number


Revision Changes Path
1.3 +8 -11 usbhostslave/RTL/hostSlaveMux/hostSlaveMux.v

http://www.opencores.org/cvsweb.shtml/usbhostslave/RTL/hostSlaveMux/hostSlaveMux.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: hostSlaveMux.v
===================================================================
RCS file: /cvsroot/sfielding/usbhostslave/RTL/hostSlaveMux/hostSlaveMux.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- hostSlaveMux.v 18 Dec 2004 14:36:12 -0000 1.2
+++ hostSlaveMux.v 20 Jan 2005 13:39:04 -0000 1.3
@@ -41,18 +41,8 @@
//// ////
//////////////////////////////////////////////////////////////////////
//
-// $Id: hostSlaveMux.v,v 1.2 2004/12/18 14:36:12 sfielding Exp $
-//
-// CVS Revision History
-//
-// $Log: hostSlaveMux.v,v $
-// Revision 1.2 2004/12/18 14:36:12 sfielding
-// Removed html documentation
-//
-// Revision 1.1.1.1 2004/10/11 04:00:56 sfielding
-// Created
-//
-//
+`timescale 1ns / 1ps
+

module hostSlaveMux (
SIEPortCtrlInToSIE,
@@ -72,6 +62,7 @@
fullSpeedBitRateFromSlave,
dataIn,
dataOut,
+ address,
writeEn,
strobe_i,
clk,
@@ -96,6 +87,7 @@
input fullSpeedBitRateFromSlave;
//hostSlaveMuxBI
input [7:0] dataIn;
+input address;
input writeEn;
input strobe_i;
input clk;
@@ -120,6 +112,7 @@
wire fullSpeedBitRateFromSlave;
//hostSlaveMuxBI
wire [7:0] dataIn;
+wire address;
wire writeEn;
wire strobe_i;
wire clk;
@@ -163,6 +156,7 @@
hostSlaveMuxBI u_hostSlaveMuxBI (
.dataIn(dataIn),
.dataOut(dataOut),
+ .address(address),
.writeEn(writeEn),
.strobe_i(strobe_i),
.clk(clk),



1.3 +12 -13 usbhostslave/RTL/hostSlaveMux/hostSlaveMuxBI.v

http://www.opencores.org/cvsweb.shtml/usbhostslave/RTL/hostSlaveMux/hostSlaveMuxBI.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: hostSlaveMuxBI.v
===================================================================
RCS file: /cvsroot/sfielding/usbhostslave/RTL/hostSlaveMux/hostSlaveMuxBI.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- hostSlaveMuxBI.v 18 Dec 2004 14:36:12 -0000 1.2
+++ hostSlaveMuxBI.v 20 Jan 2005 13:39:05 -0000 1.3
@@ -41,23 +41,15 @@
//// ////
//////////////////////////////////////////////////////////////////////
//
-// $Id: hostSlaveMuxBI.v,v 1.2 2004/12/18 14:36:12 sfielding Exp $
-//
-// CVS Revision History
-//
-// $Log: hostSlaveMuxBI.v,v $
-// Revision 1.2 2004/12/18 14:36:12 sfielding -// Removed html documentation -// -// Revision 1.1.1.1 2004/10/11 04:00:56 sfielding -// Created -// -// +`timescale 1ns / 1ps - module hostSlaveMuxBI (dataIn, dataOut, writeEn, strobe_i, clk, rst, +`include "usbHostSlave_h.v" + + module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, clk, rst, hostMode, hostSlaveMuxSel); input [7:0] dataIn; +input address; input writeEn; input strobe_i; input clk; @@ -67,6 +59,7 @@ output hostMode; wire [7:0] dataIn; +wire address; wire writeEn; wire strobe_i; wire clk; @@ -83,16 +76,19 @@ if (rst == 1'b1) hostMode <= 1'b0; else begin - if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1) + if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG ) hostMode <= dataIn[0]; end end // async read mux -always @(hostMode) +always @(address or hostMode) begin - dataOut <= {7'h0, hostMode}; + case (address) + `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode}; + `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM; + endcase end endmodule \ No newline at end of file