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From: OpenCores CVS Agent<cvs@o...>
Date: Mon Jan 17 18:27:42 CET 2005
Subject: [cvs-checkins] MODIFIED: i2s_interface ...
Date: 00/05/01 17:18:27

Modified: i2s_interface/rtl/vhdl rx_i2s_wbd.vhd tx_i2s_wbd.vhd
Log:
Bugfix of register read/write strobes


Revision Changes Path
1.3 +10 -7 i2s_interface/rtl/vhdl/rx_i2s_wbd.vhd

http://www.opencores.org/cvsweb.shtml/i2s_interface/rtl/vhdl/rx_i2s_wbd.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: rx_i2s_wbd.vhd
===================================================================
RCS file: /cvsroot/gedra/i2s_interface/rtl/vhdl/rx_i2s_wbd.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- rx_i2s_wbd.vhd 6 Aug 2004 18:55:43 -0000 1.2
+++ rx_i2s_wbd.vhd 17 Jan 2005 17:26:47 -0000 1.3
@@ -43,6 +43,9 @@
-- CVS Revision History
--
-- $Log: rx_i2s_wbd.vhd,v $
+-- Revision 1.3 2005/01/17 17:26:47 gedra
+-- Bugfix of register read/write strobes
+--
-- Revision 1.2 2004/08/06 18:55:43 gedra
-- De-linting.
--
@@ -197,19 +200,19 @@
-- read and write strobe generation

version_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXVERSION and ird = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
config_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and ird = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
config_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and iwr = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
intmask_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and ird = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
intmask_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and iwr = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
intstat_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and ird = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and iwr = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0';

end rtl;



1.3 +9 -6 i2s_interface/rtl/vhdl/tx_i2s_wbd.vhd

http://www.opencores.org/cvsweb.shtml/i2s_interface/rtl/vhdl/tx_i2s_wbd.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: tx_i2s_wbd.vhd
===================================================================
RCS file: /cvsroot/gedra/i2s_interface/rtl/vhdl/tx_i2s_wbd.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- tx_i2s_wbd.vhd 6 Aug 2004 18:55:43 -0000 1.2
+++ tx_i2s_wbd.vhd 17 Jan 2005 17:26:49 -0000 1.3
@@ -44,6 +44,9 @@
-- CVS Revision History
--
-- $Log: tx_i2s_wbd.vhd,v $
+-- Revision 1.3 2005/01/17 17:26:49 gedra
+-- Bugfix of register read/write strobes
+--
-- Revision 1.2 2004/08/06 18:55:43 gedra
-- De-linting.
--
@@ -166,17 +169,17 @@
-- read and write strobe generation

version_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXVERSION and ird = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
config_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXCONFIG and ird = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
config_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXCONFIG and iwr = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
intmask_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXINTMASK and ird = '1'
- else '0';
+ and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
intmask_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTMASK and iwr = '1'
- else '0'; + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; intstat_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and ird = '1' - else '0'; + and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and iwr = '1' else '0'; mem_wr <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and iwr = '1' else '0';