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Message
From: OpenCores CVS Agent<cvs@o...>
Date: Fri Jan 7 10:23:44 CET 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/01 07:10:23 Modified: or1k/or1200/rtl/verilog or1200_alu.v or1200_defines.v
Log:
l.ff1 and l.cmov instructions added
Revision Changes Path
1.15 +17 -5 or1k/or1200/rtl/verilog/or1200_alu.v
http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_alu.v.diff?r1=1.14&r2=1.15
(In the diff below, changes in quantity of whitespace are not shown.)
Index: or1200_alu.v
===================================================================
RCS file: /home/oc/cvs/or1k/or1200/rtl/verilog/or1200_alu.v,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -b -r1.14 -r1.15
--- or1200_alu.v 8 Jun 2004 18:17:36 -0000 1.14
+++ or1200_alu.v 7 Jan 2005 09:23:39 -0000 1.15
@@ -44,6 +44,9 @@
// CVS Revision History
//
// $Log: or1200_alu.v,v $
+// Revision 1.15 2005/01/07 09:23:39 andreje
+// l.ff1 and l.cmov instructions added
+//
// Revision 1.14 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
@@ -119,7 +122,7 @@
alu_op, shrot_op, comp_op,
cust5_op, cust5_limm,
result, flagforw, flag_we,
- cyforw, cy_we, carry
+ cyforw, cy_we, carry, flag
);
parameter width = `OR1200_OPERAND_WIDTH;
@@ -142,6 +145,7 @@
output cyforw;
output cy_we;
input carry;
+input flag;
//
// Internal wires and regs
@@ -204,6 +208,9 @@
`else
casex (alu_op) // synopsys full_case parallel_case
`endif
+ `OR1200_ALUOP_FF1: begin
+ result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
+ end
`OR1200_ALUOP_CUST5 : begin
result = result_cust5;
end
@@ -247,12 +254,17 @@
result = mult_mac_result;
end
`endif
+ `OR1200_ALUOP_CMOV: begin
+ result = flag ? a : b;
+ end
+
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
- `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
+ `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
+ begin
`endif
- result = result_and;
+ result=result_and;
end
endcase
end
1.43 +5 -1 or1k/or1200/rtl/verilog/or1200_defines.v
http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_defines.v.diff?r1=1.42&r2=1.43
(In the diff below, changes in quantity of whitespace are not shown.)
Index: or1200_defines.v
===================================================================
RCS file: /home/oc/cvs/or1k/or1200/rtl/verilog/or1200_defines.v,v
retrieving revision 1.42
retrieving revision 1.43
diff -u -b -r1.42 -r1.43
--- or1200_defines.v 8 Jun 2004 18:17:36 -0000 1.42
+++ or1200_defines.v 7 Jan 2005 09:23:39 -0000 1.43
@@ -44,6 +44,9 @@
// CVS Revision History
//
// $Log: or1200_defines.v,v $
+// Revision 1.43 2005/01/07 09:23:39 andreje
+// l.ff1 and l.cmov instructions added
+//
// Revision 1.42 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
@@ -613,7 +616,8 @@
`define OR1200_ALUOP_COMP 4'd13
`define OR1200_ALUOP_MTSR 4'd14
`define OR1200_ALUOP_MFSR 4'd15
-
+`define OR1200_ALUOP_CMOV 4'd14
+`define OR1200_ALUOP_FF1 4'd15
//
// MACOPs
//
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