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From: OpenCores CVS Agent<cvs@o...>
Date: Fri Jan 7 09:46:03 CET 2005
Subject: [cvs-checkins] MODIFIED: simple_fm_receiver ...
Date: 00/05/01 07:09:46

Modified: simple_fm_receiver/bench input_fm.vhdl
Log:
Fix elsif and if statement




Revision Changes Path
1.2 +6 -6 simple_fm_receiver/bench/input_fm.vhdl

http://www.opencores.org/cvsweb.shtml/simple_fm_receiver/bench/input_fm.vhdl.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: input_fm.vhdl
===================================================================
RCS file: /cvsroot/arif_endro/simple_fm_receiver/bench/input_fm.vhdl,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- input_fm.vhdl 4 Jan 2005 02:05:56 -0000 1.1
+++ input_fm.vhdl 7 Jan 2005 08:45:59 -0000 1.2
@@ -1,4 +1,4 @@
--- $Id: input_fm.vhdl,v 1.1 2005/01/04 02:05:56 arif_endro Exp $
+-- $Id: input_fm.vhdl,v 1.2 2005/01/07 08:45:59 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Input signal FM
-- Project : FM Receiver
@@ -93,15 +93,15 @@
-- if (clear = '1') then
-- counter (09 downto 0) <= (others => B"0000000000");
-- elsif (((clock = '1') and clock'event) and (not(clear = '1')) then
- if (((clock = '1') and (not( clear = '1'))) and clock'event) then
+ if (clear = '1') then
+ counter <= (others => '0');
+ test_signal_fm <= (others => '0');
+ test_signal_fmTri <= (others => '0');
+ elsif (((clock = '1') and (not( clear = '1'))) and clock'event) then
counter(09 downto 0) <= counter_tmp(09 downto 0);
-- clock_out <= clock;
test_signal_fm <= test_signal_fm_int;
test_signal_fmTri <= test_signal_fmTri_int;
- elsif (clear = '1') then
- counter <= (others => '0');
- test_signal_fm <= (others => '0');
- test_signal_fmTri <= (others => '0');
end if;
end process;