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Message
From: OpenCores CVS Agent<cvs@w...>
Date: Fri May 21 14:35:22 CEST 2004
Subject: [cvs-checkins] uart16550/rtl/verilog uart_wb.v
CVSROOT: /home/oc/cvs
Module name: uart16550
Changes by: tadejm 04/05/21 14:35:20
Modified files:
rtl/verilog : uart_wb.v
Log message:
Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode.
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